Abstract: According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Abstract: An embodiment asynchronous finite state machine (AFSM) circuit includes a first state register configured to output a first state acknowledgment signal in response to the AFSM circuit transitioning to a first state, a second state register configured to output a second state acknowledgment signal in response to the AFSM circuit transitioning to a second state, a first acknowledgement branch configured to convey the second state acknowledgment signal from the second state register to the first state register, a second acknowledgement branch configured to convey the first state acknowledgment signal from the first state register to the second state register, and transition logic circuitry.

Abstract: According to an embodiment, a demodulator circuit for wireless power transfer systems addresses phase wrap-around issues in phase-shift keying (PSK) modulated signals. The demodulator converts received signals from Cartesian to polar coordinates. It performs phase correction to mitigate rapid fluctuations when the signal constellation approaches the negative real axis in the IQ plane. Phase correction techniques include applying a counter-controlled offset to rotate the constellation, removing the DC component using an exponential moving average filter, or employing a differential comb filter. The demodulator improves reliability in decoding backscatter communication from power receivers to transmitters, enhancing performance across various operating conditions and circuit configurations in wireless charging applications.

Abstract: A method of digital signal processing includes applying a first infinite impulse response filtering operation to a digital input signal to produce a first filtered signal, performing a mathematical transformation on a combination of the digital input signal and the first filtered signal to produce a transformed signal, applying a second infinite impulse response filtering operation to the transformed signal to produce a second filtered signal, performing a scaling operation on the second filtered signal to produce a scaled signal, and combining the second filtered signal and the scaled signal to produce a digital output signal indicative of a statistical property of the digital input signal.

Abstract: According to an embodiment, a test system for serially testing of finite state machine circuits using scan chains is proposed. Each scan chain is coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto. Each scan chain has a number of input terminals and one output terminal. The test system includes a dispatcher input interface with a number of input terminals and multiple sets of output terminals, where each set of output terminals includes multiple output terminals coupled to the input terminals of an associated scan chain. The test system further includes a dispatcher output interface with multiple input terminals and one output terminal. The output terminal of each scan chain is coupled to one of the input terminals of the dispatcher output interface.

Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree.

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree.

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.