Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region a heater structure is first formed and a phase change layer is deposited on and in contact with the heater structure. Then, the phase change layer and the heater structure are defined by subsequent self-aligned etch steps.

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract: In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

Abstract: A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a semiconductor substrate and are spaced from one another via a channel region, and by an isolated control region connected to a respective row and overlying the channel region. The first conductive region is connected to a connection line extending parallel to the rows, the second conductive region is connected to the phase-change region, and the phase-change region is connected to a respective column. The first connection line is a metal interconnection line and is connected to the first conductive region via a source-contact region made as point contact and distinct from the first connection line.

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.

Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a predetermined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

Abstract: A magnetic random access memory (MRAM) device has increased ?R/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ?R/R. The plural transistors can share a source region.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract: The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract: A process for manufacturing a memory device having selector bipolar transistors for storage elements, includes the steps of: in a semiconductor body, forming at least a selector transistor, having at least an embedded conductive region, and forming at least a storage element, stacked on and electrically connected to the selector transistor; moreover, the step of forming at least a selector transistor includes forming at least a raised conductive region located on and electrically connected to the embedded conductive region.

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.