Patents by Inventor Roberto Bonetti

Roberto Bonetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for the preparation of tetraconazole
    Patent number: 9884829
    Abstract: The present invention relates to a new process for the preparation of Tetraconazole or one of its optically active isomers by means of the fluorination of 2-(2,4-dichlorophenyl)-3-(1H-1,2,4-triazol-1-yl)propan-1-ol.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: February 6, 2018
    Assignee: ISAGRO S.P.A.
    Inventors: Roberto Bonetti, Giampaolo Zanardi
  • PROCESS FOR THE PREPARATION OF TETRACONAZOLE
    Publication number: 20170327473
    Abstract: The present invention relates to a new process for the preparation of Tetraconazole or one of its optically active isomers by means of the fluorination of 2-(2,4-dichlorophenyl)-3-(1H-1,2,4-triazol-1-yl)propan-1-ol.
    Type: Application
    Filed: December 12, 2014
    Publication date: November 16, 2017
    Inventors: Roberto BONETTI, Giampaolo ZANARDI
  • Device and method for writing/reading a memory register shared by a plurality of peripherals
    Patent number: 9032120
    Abstract: A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Roberto Bonetti
  • DEVICE AND METHOD FOR WRITING/READING A MEMORY REGISTER SHARED BY A PLURALITY OF PERIPHERALS
    Publication number: 20140115200
    Abstract: A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 24, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventor: Roberto Bonetti
  • Interrupt management unit and a method for identifying an interrupt request having the highest priority
    Patent number: 5758167
    Abstract: A management unit for microcontrollers equipped with a decoder for a plurality of interrupt channels, the unit being connected to a central processing unit of the microcontroller to decode and transfer thereto a single interrupt digital signal through the decoder, and comprises a first circuit portion for selecting homolog pairs of channels incorporating a modular chain of elements, each having a respective channel pair connected thereto. The first or selection portion is associated with a second decoding circuit portion, and the interrupt signal is a reform of the channel interrupt vector carrying higher priority in the channel pair selected by the chain.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: May 26, 1998
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Roberto Bonetti