Patents by Inventor Roberto Colombo

Roberto Colombo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200198779
    Abstract: A rotor for an aircraft is described that comprises: a hub rotatable about an axis and, in turn, comprising a plurality of blades; a mast connectable to a drive member of the aircraft and connected to the hub to drive the hub in rotation about the axis; and damping means to dampen the transmission of vibrations to the mast in a plane orthogonal to the axis; the damping means comprising at least a first mass and a second mass that can eccentrically rotate about the axis with a first and a second speed of rotation, respectively; the first mass and second mass are operatively connected to the mast to generate, respectively, a first and a second damping force on the mast having a main component in a direction radial to the axis; the rotor comprises a transmission unit, which is interposed between the mast and the first and second masses so as to drive the first and second masses in rotation.
    Type: Application
    Filed: June 28, 2018
    Publication date: June 25, 2020
    Inventors: Attilio Colombo, Luigi Bottasso, Paolo Pisani, Andrea Favarotto, Dario Colombo, Federico Montagna, Roberto Regonini, Francesco Braghin, Simone Cinquemani
  • Publication number: 20200167220
    Abstract: A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 28, 2020
    Inventor: Roberto Colombo
  • Publication number: 20200169459
    Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 28, 2020
    Inventor: Roberto Colombo
  • Patent number: 10647159
    Abstract: A tyre for vehicle wheels having a tread pattern includes: a) two circumferential grooves, which define a first and a second shoulder region, and one central region; b) a plurality of asymmetric transverse grooves having a substantially ā€œVā€ shape, which extend for the whole width of the tread, including an alternate sequence of a first and a second asymmetric transverse groove defining an alternate sequence of a first and a second asymmetric module; and c) a plurality of lateral transverse grooves, which includes one first lateral transverse groove extending for the whole width of the first shoulder region and for a portion of the central region of the first asymmetric modules, and one second lateral transverse groove extending for the whole width of the second shoulder region and for a portion of the central region of the second asymmetric modules.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 12, 2020
    Assignee: PIRELLI TYRE S.p.A.
    Inventors: Gianfranco Colombo, Stefano Montesello, Roberto Sangalli
  • Patent number: 10526892
    Abstract: A turbine of an organic Ranking cycle (ORC) is described. The turbine includes a shaft supported by at least two bearings and a plurality of axial stages of expansion, defined by arrays of stator blades alternated with arrays or rotor blades. The rotor blades are sustained by corresponding supporting disks. A main supporting disk is directly coupled to the shaft in an outer position with respect to the bearings, and the remaining supporting disks are constrained to the main supporting disk, and one to the other in succession, but not directly to the shaft. Some of the remaining supporting disks are constrained to the main supporting disk and cantileverly extend from the same side of the bearings that support the shaft, so that the center of gravity of the rotor part of the turbine is shifted more towards the bearings.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 7, 2020
    Assignee: TURBODEN SPA
    Inventors: Roberto Bini, Mario Gaia, Davide Colombo
  • Publication number: 20190272210
    Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 5, 2019
    Inventor: Roberto Colombo
  • Publication number: 20190272211
    Abstract: A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 5, 2019
    Inventor: Roberto Colombo
  • Publication number: 20190258493
    Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration da
    Type: Application
    Filed: February 12, 2019
    Publication date: August 22, 2019
    Inventors: Roberto Colombo, Om RANJAN
  • Publication number: 20190227747
    Abstract: A processing system includes a plurality of configuration data clients, each of the plurality of configuration data clients having a register and being associated with a respective address. The system includes a non-volatile memory with configuration data for each of the plurality of configuration data clients. The configuration data is stored as data packets having an attribute field identifying the respective address of the plurality of configuration data clients and the respective configuration data. A hardware configuration circuit is configured to sequentially read the data packets from the non-volatile memory and transmit the respective configuration data read from the non-volatile memory to the respective configuration data client. The configuration data client is configured to receive a first set of configuration data addressed to the respective address from the hardware configuration circuit and store the first set of configuration data in the respective register.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 25, 2019
    Inventor: Roberto Colombo
  • Publication number: 20190152270
    Abstract: A tyre for vehicle wheels having a tread pattern includes: a) two circumferential grooves, which define a first and a second shoulder region, and one central region; b) a plurality of asymmetric transverse grooves having a substantially ā€œVā€ shape, which extend for the whole width of the tread, including an alternate sequence of a first and a second asymmetric transverse groove defining an alternate sequence of a first and a second asymmetric module; and c) a plurality of lateral transverse grooves, which includes one first lateral transverse groove extending for the whole width of the first shoulder region and for a portion of the central region of the first asymmetric modules, and one second lateral transverse groove extending for the whole width of the second shoulder region and for a portion of the central region of the second asymmetric modules.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: Pirelli Tyre S.p.A.
    Inventors: Gianfranco COLOMBO, Stefano Montesello, Roberto Sangalli
  • Publication number: 20190136704
    Abstract: A mixed flow turbine (1) for the expansion phase of steam thermodynamic cycles of an organic Rankine cycle provided with a first section (A) in which a first expansion of a main flow of working fluid takes place, in a substantially radial direction having at least one stator stage (S1, S2, . . . Sn) and at least one rotor stage (R1, R2, . . . Rn) of a second section (B) in which a second expansion of the main flow of the working fluid takes place in a substantially axial direction having at least one stator stage and at least one rotor stage and, between the first and the second section, with at least one angular stator stage (S4) comprising an array of angular blades which deflect the main flow of working fluid from the initial radial direction to a substantially axial direction. The turbine (1) is provided with means for injection (60) and/or means for extraction (70) of a second flow of working fluid, placed in proximity of the stator stage (S4).
    Type: Application
    Filed: May 8, 2017
    Publication date: May 9, 2019
    Applicant: TURBODEN S. p. A.
    Inventors: Mario Gaia, Roberto Bini, Davide Colombo
  • Publication number: 20190026498
    Abstract: In an embodiment, a processing system includes a non-volatile memory, a hardware block, a protection circuit associated with the hardware block, and a password verification circuit. The non-volatile memory stores at least one reference password. The password verification circuit is configured to receive a password verification command, obtain a reference password, and test whether the passwords correspond. In case the passwords correspond, the password verification circuit generate an overwrite signal. The protection circuit is configured to receive a control command and selectively forward the control command to the associated hardware block as a function of the overwrite signal.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 24, 2019
    Inventor: Roberto Colombo
  • Publication number: 20190007201
    Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Roberto Colombo, Guido Marco Bertoni, William Orlando, Roberta Vittimani
  • Publication number: 20190007202
    Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Roberto Colombo, Guido Marco Bertoni, William Orlando, Roberta Vittimani
  • Publication number: 20180357015
    Abstract: A processing system includes a processing unit and a hardware block configured to change operation as a function of life cycle data. A one-time programmable memory includes original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory and provide the original life cycle data to the hardware block. The hardware configuration module includes a register providing the life cycle data used to change operation of the hardware block. The hardware configuration module is configured to store the original life cycle data in the register and receive a command from the processing unit. The command includes a write request for storing new life cycle data in the register.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 13, 2018
    Inventor: Roberto Colombo
  • Publication number: 20180357012
    Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 13, 2018
    Inventor: Roberto Colombo
  • Publication number: 20180329774
    Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 15, 2018
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
  • Publication number: 20180330127
    Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 15, 2018
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio
  • Publication number: 20180330123
    Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 15, 2018
    Inventors: Roberto COLOMBO, Nicolas BERNARD GROSSIER, Giovanni DISIRIO, Lorenzo RE FIORENTIN
  • Patent number: D861577
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 1, 2019
    Assignee: PIRELLI TYRE S.P.A.
    Inventors: Gianfranco Colombo, Roberto Bolzoni, Stefano Bizzi, Daniele Lorenzetti