Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

Abstract: A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.

Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

Abstract: A processing system comprises a processing unit, a hardware block configured to change operation as a function of life cycle data, and a one-time programmable memory storing original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory, to store the original life cycle data in a register, to receive a write request from the processing unit, and to selectively execute the write request to overwrite the original life cycle data with new life cycle data in the register.

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.