Abstract: A processing system includes a non-volatile memory including a first memory slot arranged to store a first master password, a second memory slot arranged to store a second master password and a third memory slot arranged to store a security password. A password verification circuit is configured to set an overwrite signal to indicate a success verification of the first master password or a success verification of the second master password. A protection circuit is configured to manage write access to the third memory slot arranged to store a security password. The protection circuit receives a write request for writing a new security password to the third memory slot. The protection circuit determines whether security access data indicate that the third memory slot is associated with the first master password or with the second master password, and determines whether the overwrite signal indicates a success verification of the first master password or the second master password.

Abstract: According to an embodiment, an interrupt checker circuit includes a timestamp checker circuit having a first input terminal coupled to an interrupt signal. A second input terminal of the timestamp checker circuit is configured to receive a global time reference. The timestamp checker circuit is configured to record a first timestamp corresponding to a first interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, record a second timestamp corresponding to a second interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, and compare a time difference between the second timestamp and the first timestamp to an expected duration and, based thereon, generate an error signal in response to the time difference being outside the expected duration.

Abstract: A processing system includes a hardware address protection for limiting access to communication system addresses based on a virtual machine ID (VMID), a plurality of processing cores, a volatile memory, a hardware secure module (HSM), and a further communication system connecting the HSM to the communication system. A slave interface circuit of the further communication system receives a write request from the communication system and transmits the VMID in the write request to the HSM. The HSM accesses virtual machine configuration data to determine address data indicating positions of first and second memory areas in the volatile memory, and sends, via a master interface circuit, read/write requests, including the VMID, to the communication system to read command data from the first memory area and write response data to the second memory area. The HSM then stores a response notification to a register of the further communication system.

Abstract: The present disclosure relates to a processing system comprising a plurality of safety monitoring circuits and a fault collection and error management circuit configured to generate one or more reaction signals as a function of error signals provided by the safety monitoring circuits. The fault collection and error management circuit comprises a sequential logic circuit supplied by a first supply voltage and driven by a first clock signal, and a pulse generator circuit configured to generate a trigger signal in response to the first clock signal. The processing system also comprises first and second monitoring circuits and a combinational logic circuit. In response to determining that first or second error signals are asserted by the first or second monitoring circuits, respectively, the combinational logic circuit asserts a third error signal.

Abstract: A processing system includes a memory controller subsystem connected to a communication channel configured to be connected to an external memory, wherein the communication channel comprises a data signal, and a master circuit is configured to send write and read requests to the memory subsystem. The memory controller subsystem comprises first and second memory controllers. In response to receiving a write request, each memory controller generates a respective first or second communication for storing the respective data to the respective memory address by generating a respective first or second data signal used to transmit the respective memory address and the respective data. Conversely, in response to receiving a read request, each memory controller generates the respective first or second communication for receiving data associated with the respective memory address by generating the respective first or second data signal to transmit the respective memory address and receive the respective data.

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

Abstract: In accordance with various embodiments of the present disclosure, a processing system is provided. In some embodiments, the processing system comprises a non-secure processing unit and a cryptographic coprocessing unit. The cryptographic coprocessing unit comprises a data interface and a hardware cryptographic engine. The data interface is configured to receive, from the non-secure processing unit, one or more control blocks and one or more data block. The hardware cryptographic engine is configured to process, as a function of a cryptographic key, the one or more control blocks and the one or more data blocks received by the data interface. The data interface is configured to receive a first control block from the non-secure processing unit, latch the received first control block, receive a first data block from the non-secure processing unit and transfer the latched first control block and the received first data block to the hardware cryptographic engine.

Abstract: A processing system includes a hardware address protection for limiting access to communication system addresses based on a virtual machine ID (VMID), a plurality of processing cores, a volatile memory, a hardware secure module (HSM), and a further communication system connecting the HSM to the communication system. A slave interface circuit of the further communication system receives a write request from the communication system and transmits the VMID in the write request to the HSM. The HSM accesses virtual machine configuration data to determine address data indicating positions of first and second memory areas in the volatile memory, and sends, via a master interface circuit, read/write requests, including the VMID, to the communication system to read command data from the first memory area and write response data to the second memory area. The HSM then stores a response notification to a register of the further communication system.

Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.

Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.