Abstract: An optoelectronic semiconductor chip comprises a semiconductor body including a plurality of active regions configured to generate electromagnetic radiation, the plurality of active regions being arranged in a horizontal plane. The optoelectronic semiconductor chip further comprises a conductive member configured to electrically connect at least two adjacent ones of the active regions with each other, the conductive member being arranged over a first main surface of the semiconductor body. The optoelectronic semiconductor chip further comprises a contact element extending from the first main surface to a second main surface of the semiconductor body and being electrically connected to at least one of the active regions via a contact material over the first main surface, and an optical element arranged over the first main surface of the semiconductor body.

Abstract: A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other, each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit, wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.

Abstract: An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the at least one booster and associated therewith in a “system in a package configuration.

Abstract: A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other, each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit, wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.

Abstract: A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of the first side or the second side of the semiconductor device along a second direction. The chip level contact portions extend along the first direction. Ends of the chip level contact portions are aligned along a line extending along the second direction. This leadframe can be included with a semiconductor chip in a packaged integrated circuit.

Abstract: A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of the first side or the second side of the semiconductor device along a second direction. The chip level contact portions extend along the first direction. Ends of the chip level contact portions are aligned along a line extending along the second direction. This leadframe can be included with a semiconductor chip in a packaged integrated circuit.

Abstract: A low supply voltage memory device includes a first supply pin and a second supply pin for the connection to a first supply voltage source (VDD) and to a second supply voltage source (VDDQ). The device may include a memory and at least one booster overlapped by way of a “system in package” system and in particular with “stacked-die” technology. This booster may be connected to the memory by way of a plurality of discrete components.