Abstract: Methods, systems, and devices for reliable and efficient boot logical unit access are described. For instance, a memory device may receive a request to write data to a boot logical unit of the memory device. The memory device may update a parameter from a first value to a second value based on receiving the request, the second value indicating a first stage of a procedure for updating the boot logical unit. The memory device may write, to a block of memory in the memory device, the data based on the parameter indicating the first stage of the procedure. Additionally or alternatively, the memory device may read a value of the parameter as part of a power up procedure and may perform a boot procedure using either first data at the boot logical unit or second data at the block of memory based on reading the value of the parameter.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

Abstract: Disclosed herein are methods, apparatuses and systems related to adjusting memory operations according to a usage pattern or a contextual parameter. The apparatus may be configured to track an operating measure associated with operating in an active operating mode and a switching measure associated with a transition into a reduced power mode. Based on the tracked measures, the apparatus may be configured to dynamically adjust a delay used in subsequently transitioning into the reduced power mode.

Abstract: Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.

Abstract: Methods, systems, and devices for memory management during suspend and resume operations are described. In some examples, a memory system may receive an indication of a range of addresses for storing an image of a host system. In some cases, the host system may indicate a logical unit that is dedicated for suspend and resume operations. In some other cases, the memory system may receive a command indicating that the host system is in a suspend state or a resume state for a duration. In response to the command, the memory system may track accesses to the non-volatile media during the duration to determine the range of addresses associated with the image of the host system. Additionally, the memory system may implement one or more write optimizations, read optimizations, or both, to further improve the performance of the memory system during suspend and resume operations.

Abstract: Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Abstract: Methods, systems, and devices for out-of-order per-zone command handling for zoned memory are described. Commands for one or more zones of multiple zones of a memory space may be loaded into a queue. Based on loading the commands, an execution of a first command of first commands received for a first zone may be delayed based on an address of the first command being different than a current reference address of a pointer for the first zone. Based on delaying the first command, a subsequent command of the first commands may be executed based on being loaded into the queue within a threshold duration of the first command and an address of the second command matching the current reference address of the pointer. Based on executing the second command, the first command may be executed based on the first address matching the current reference address of the pointer.

Abstract: Methods, systems, and devices for reliable and efficient boot logical unit access are described. For instance, a memory device may receive a request to write data to a boot logical unit of the memory device. The memory device may update a parameter from a first value to a second value based on receiving the request, the second value indicating a first stage of a procedure for updating the boot logical unit. The memory device may write, to a block of memory in the memory device, the data based on the parameter indicating the first stage of the procedure. Additionally or alternatively, the memory device may read a value of the parameter as part of a power up procedure and may perform a boot procedure using either first data at the boot logical unit or second data at the block of memory based on reading the value of the parameter.

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Abstract: Various aspects of the present disclosure relate to enabling a memory system to support compressing entries of a change log and improving the efficiency of the memory system by enabling the memory system changes associated with the change log to occur concurrently. Either a “staged” compression technique or a “direct” compression technique may be used to compress entries of the change log. In the case of a staged compression, the memory system may merge a new entry with a staged entry, may update the previously-staged entry, and may subsequently release the merged entry to the change log. In the case of a direct compression, the memory system may decide whether the backend entry can be directly merged with existing entries of the change log.

Abstract: Methods, systems, and devices for an intelligent throughput router are described. A memory system may monitor parameters associated with write commands being received. The memory system may select whether to write data to a first block type (e.g., a high density cell block) or a second block type (e.g., a single-level cell block) of a non-volatile memory device based on the parameters. The memory system may store data associated with write commands in a volatile storage area such as a write buffer, and monitor the size of the write buffer. The memory system may select the first block type or the second block type based on thresholds associated with usage of the write buffer. The memory system may estimate a throughput of data associated with the write commands, and select the first block type or the second block type based on thresholds associated with the throughput of data.

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.