Abstract: A converter system is disclosed. The converter system including a system controller; a plurality of circuit elements configured to operate in response to control signals from the system controller; a bus controller configured to transmit data to a communication bus; and a plurality of power converters, each including a digital to analog converter (DAC) configured to generate an analog voltage for one or more of the circuit elements based on a digital signal on the communication bus; a digital module configured to receive digital data from the bus controller on the communication bus; and an amplifier, configured to adjust an offset according to an offset compensation code received from the digital module.

Abstract: An integrated circuit includes N analog circuit blocks, a bidirectional M-bit parallel data bus coupled to each of the N analog circuit blocks, an external data port, and an interface circuit coupled to the external data port and the bidirectional M-bit parallel data bus. Each analog block includes at most X data registers. The interface circuit includes an analog block selection output, a register selection output, and a mode selection output, each coupled to each of the N analog circuit blocks. The analog block selection output is configured to select an analog block using at most N signals. The register selection output is configured to select a register using at most X signals. The mode selection output is configured to control the direction of data flow between the analog blocks and the interface circuit on the data bus.

Abstract: A converter system is disclosed. The converter system including a system controller; a plurality of circuit elements configured to operate in response to control signals from the system controller; a bus controller configured to transmit data to a communication bus; and a plurality of power converters, each including a digital to analog converter (DAC) configured to generate an analog voltage for one or more of the circuit elements based on a digital signal on the communication bus; a digital module configured to receive digital data from the bus controller on the communication bus; and an amplifier, configured to adjust an offset according to an offset compensation code received from the digital module.

Abstract: A clock signal constituted by pulses with given frequency of repetition and a data signal is able to assume two logic levels are transmitted simultaneously on a two-wire line in the form of a bipolar differential pulse signal with frequency of repetition of the pulses equal to the frequency of repetition of the pulses of the clock signal and in which the sign of the pulses of the pulse signal applied to said two-wire line varies according to the logic level of the data signal.