Patents by Inventor Roberto Nonis

Roberto Nonis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11233520
    Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: January 25, 2022
    Assignee: Infineon Technologies AG
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Publication number: 20210036710
    Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Patent number: 10826508
    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Publication number: 20190081633
    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Patent number: 10135452
    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 20, 2018
    Assignees: Infineon Technologies AG, Politecnico Di Milano
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Publication number: 20180241406
    Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
  • Patent number: 9985639
    Abstract: Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Peter Thurner, Thomas Santa
  • Publication number: 20170194976
    Abstract: Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: Roberto NONIS, Peter THURNER, Thomas SANTA
  • Patent number: 9577622
    Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Nicola Da Dalt, Roberto Nonis, Thomas Santa
  • Patent number: 9571108
    Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
  • Patent number: 9258110
    Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 9, 2016
    Assignee: Infineon Technologies AG
    Inventors: Werner Grollitsch, Roberto Nonis
  • Publication number: 20150326203
    Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.
    Type: Application
    Filed: May 7, 2015
    Publication date: November 12, 2015
    Inventors: Nicola DA DALT, Roberto NONIS, Thomas SANTA
  • Publication number: 20150318980
    Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Inventors: Werner Grollitsch, Roberto Nonis
  • Patent number: 9148101
    Abstract: At least one implementation relates to a method that includes receiving a bias voltage provided by a low-dropout voltage regulator (LDO) error amplifier; supplying a feedback voltage to the LDO error amplifier; supplying a power signal to a load; and providing a control signal to enable or disable the load and enable or disable the LDO error amplifier.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: September 29, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Roberto Nonis, Nicola Da Dalt
  • Publication number: 20150070060
    Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
  • Patent number: 8890592
    Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.
    Type: Grant
    Filed: October 13, 2012
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
  • Patent number: 8779867
    Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 15, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Edwin Thaller, Roberto Nonis
  • Patent number: 8742858
    Abstract: Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Nicola DaDalt
  • Publication number: 20140103976
    Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.
    Type: Application
    Filed: October 13, 2012
    Publication date: April 17, 2014
    Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
  • Publication number: 20130107978
    Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Applicant: Intel Mobile Communications GmbH
    Inventors: Edwin Thaller, Roberto Nonis