Patents by Inventor Roberto Nonis
Roberto Nonis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11233520Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.Type: GrantFiled: October 16, 2020Date of Patent: January 25, 2022Assignee: Infineon Technologies AGInventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Publication number: 20210036710Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Patent number: 10826508Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: GrantFiled: November 13, 2018Date of Patent: November 3, 2020Assignee: Infineon Technologies AGInventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Publication number: 20190081633Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Patent number: 10135452Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: GrantFiled: February 21, 2017Date of Patent: November 20, 2018Assignees: Infineon Technologies AG, Politecnico Di MilanoInventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Publication number: 20180241406Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Patent number: 9985639Abstract: Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.Type: GrantFiled: January 5, 2016Date of Patent: May 29, 2018Assignee: Infineon Technologies AGInventors: Roberto Nonis, Peter Thurner, Thomas Santa
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Publication number: 20170194976Abstract: Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.Type: ApplicationFiled: January 5, 2016Publication date: July 6, 2017Inventors: Roberto NONIS, Peter THURNER, Thomas SANTA
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Patent number: 9577622Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.Type: GrantFiled: May 7, 2015Date of Patent: February 21, 2017Assignee: Infineon Technologies AGInventors: Nicola Da Dalt, Roberto Nonis, Thomas Santa
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Patent number: 9571108Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: GrantFiled: November 17, 2014Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 9258110Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.Type: GrantFiled: April 30, 2014Date of Patent: February 9, 2016Assignee: Infineon Technologies AGInventors: Werner Grollitsch, Roberto Nonis
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Publication number: 20150326203Abstract: Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.Type: ApplicationFiled: May 7, 2015Publication date: November 12, 2015Inventors: Nicola DA DALT, Roberto NONIS, Thomas SANTA
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Publication number: 20150318980Abstract: A phase detector device having a modulo N operator coupled with an adder is disclosed. Furthermore, clock recovery devices using such a phase detector device are discussed.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Inventors: Werner Grollitsch, Roberto Nonis
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Patent number: 9148101Abstract: At least one implementation relates to a method that includes receiving a bias voltage provided by a low-dropout voltage regulator (LDO) error amplifier; supplying a feedback voltage to the LDO error amplifier; supplying a power signal to a load; and providing a control signal to enable or disable the load and enable or disable the LDO error amplifier.Type: GrantFiled: January 29, 2013Date of Patent: September 29, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Roberto Nonis, Nicola Da Dalt
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Publication number: 20150070060Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 8890592Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: GrantFiled: October 13, 2012Date of Patent: November 18, 2014Assignee: Infineon Technologies AGInventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Patent number: 8779867Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.Type: GrantFiled: October 26, 2011Date of Patent: July 15, 2014Assignee: Intel Mobile Communications GmbHInventors: Edwin Thaller, Roberto Nonis
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Patent number: 8742858Abstract: Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator.Type: GrantFiled: January 28, 2011Date of Patent: June 3, 2014Assignee: Infineon Technologies AGInventors: Roberto Nonis, Nicola DaDalt
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Publication number: 20140103976Abstract: Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.Type: ApplicationFiled: October 13, 2012Publication date: April 17, 2014Inventors: Roberto Nonis, Nicola DaDalt, Edwin Thaller
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Publication number: 20130107978Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: Intel Mobile Communications GmbHInventors: Edwin Thaller, Roberto Nonis