Patents by Inventor Roberto Quaglino

Roberto Quaglino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707767
    Abstract: Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cesar Augusto Braz, Roberto Quaglino
  • Publication number: 20200177090
    Abstract: Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 4, 2020
    Inventors: Cesar Augusto Braz, Roberto Quaglino
  • Patent number: 10056844
    Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 21, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Roberto Quaglino, Giuseppe Bernacchia
  • Patent number: 9979309
    Abstract: In one example, a circuit for controlling synchronous rectification includes a first current compensation module, a second current compensation module, and a control module. The first current compensation module is configured to provide a first current into parasitic capacitance at a drain pin when a drain of a synchronous rectifier draws current from the parasitic capacitance. The drain pin is coupled to the drain of the synchronous rectifier via a resistor. The first current compensation module is further configured to generate a triggering signal using the first current. The second current compensation module is configured to draw a second current from the parasitic capacitance when the drain of the synchronous rectifier provides current into the parasitic capacitance and generate an arming signal using the second current. The control module is configured to activate the synchronous rectifier using the triggering signal and the arming signal.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Green, Hongying Ding, Roberto Quaglino
  • Publication number: 20170310230
    Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 26, 2017
    Inventors: Roberto Quaglino, Giuseppe Bernacchia
  • Patent number: 9716439
    Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 25, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Roberto Quaglino, Giuseppe Bernacchia
  • Publication number: 20160226389
    Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: Roberto Quaglino, Giuseppe Bernacchia
  • Patent number: 6822401
    Abstract: A method manages lamp fault conditions in electronic ballasts for one or more gas discharge lamps. The method for fault management of electronic ballast for at least one gas discharge lamp includes the steps of: preheating the lamp filaments applying a low current for a predetermined time; igniting the lamp by increasing at a predetermined rate the voltage applied up to a predetermined strike value; monitoring the lamp current; repeating the steps of igniting the lamp and monitoring the lamp current for a predetermined numbers of times if the lamp current is over a predetermined threshold; and powering the lamp at normal operating conditions.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: November 23, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavia Borella, Ugo Moriconi, Albino Pidutti, Roberto Quaglino, Francesca Sandrini
  • Publication number: 20030006720
    Abstract: A method manages lamp fault conditions in electronic ballasts for one or more gas discharge lamps. The method for fault management of electronic ballast for at least one gas discharge lamp includes the steps of: preheating the lamp filaments applying a low current for a predetermined time; igniting the lamp by increasing at a predetermined rate the voltage applied up to a predetermined strike value; monitoring the lamp current; repeating the steps of igniting the lamp and monitoring the lamp current for a predetermined numbers of times if the lamp current is over a predetermined threshold; and powering the lamp at normal operating conditions.
    Type: Application
    Filed: January 24, 2002
    Publication date: January 9, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Flavia Borella, Ugo Moriconi, Albino Pidutti, Roberto Quaglino, Francesca Sandrini
  • Patent number: 6487059
    Abstract: The power supply device includes a DC-DC converter circuit having a power switch and a driving stage. The driving stage has a compensation terminal on which a compensation voltage is present, and which receives a biasing current. The driving stage includes a control circuit having an output terminal connected to a control terminal of the power switch and disconnection-detecting circuitry connected to the compensation terminal and generating a signal for permanent turning-off of the power switch when the biasing current drops below a current-threshold value. The driving stage moreover includes over-voltage detecting circuitry connected to the compensation terminal and generating a signal for temporary turning-off of the power switch when the compensation voltage exceeds a voltage-threshold value.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: November 26, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gregorio Bontempo, Claudio Adragna, Mauro Fagnani, Albino Pidutti, Francesco Pulvirenti, Roberto Quaglino, Giuseppe Gattavari
  • Publication number: 20020044463
    Abstract: The power supply device comprises a DC-DC converter circuit including a power switch and a driving stage. The driving stage has a compensation terminal on which a compensation voltage is present and which receives a biasing current, said driving stage comprising a control circuit having an output terminal connected to a control terminal of the power switch and disconnection-detecting means connected to said compensation terminal and generating a signal for permanent turning-off of said power switch when the biasing current drops below a current-threshold value. The driving stage moreover comprises over-voltage detecting means connected to the compensation terminal and generating a signal for temporary turning-off of said power switch when said compensation voltage exceeds a voltage-threshold value.
    Type: Application
    Filed: July 30, 2001
    Publication date: April 18, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Gregorio Bontempo, Claudio Adragna, Mauro Fagnani, Albino Pidutti, Francesco Pulvirenti, Roberto Quaglino, Giuseppe Gattavari