Patents by Inventor Roberto Quaglino
Roberto Quaglino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10707767Abstract: Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.Type: GrantFiled: December 4, 2018Date of Patent: July 7, 2020Assignee: Infineon Technologies Austria AGInventors: Cesar Augusto Braz, Roberto Quaglino
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Publication number: 20200177090Abstract: Techniques are provided for avoiding an avalanche breakdown voltage across a synchronous rectification (SR) switch on the secondary side of an isolated switched-mode power converter operating in a low-power mode, e.g., a burst mode, during which a load of the power converter draws negligible current. This is accomplished via use of a two-level switch driver for controlling a power switch on the primary side of the power converter. The two-level switch driver is configured to source low current levels to a control terminal (e.g., gate) of the power switch during burst-mode operation. This low current reduces the slope of the rising edge of voltage pulses on the primary and secondary sides of the power converter which, in turn, limits the peak of the voltage ringing across the SR switch. By limiting the voltage in this manner, the SR switch avoids entering avalanche breakdown.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Inventors: Cesar Augusto Braz, Roberto Quaglino
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Patent number: 10056844Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.Type: GrantFiled: June 16, 2017Date of Patent: August 21, 2018Assignee: Infineon Technologies Austria AGInventors: Roberto Quaglino, Giuseppe Bernacchia
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Patent number: 9979309Abstract: In one example, a circuit for controlling synchronous rectification includes a first current compensation module, a second current compensation module, and a control module. The first current compensation module is configured to provide a first current into parasitic capacitance at a drain pin when a drain of a synchronous rectifier draws current from the parasitic capacitance. The drain pin is coupled to the drain of the synchronous rectifier via a resistor. The first current compensation module is further configured to generate a triggering signal using the first current. The second current compensation module is configured to draw a second current from the parasitic capacitance when the drain of the synchronous rectifier provides current into the parasitic capacitance and generate an arming signal using the second current. The control module is configured to activate the synchronous rectifier using the triggering signal and the arming signal.Type: GrantFiled: July 19, 2017Date of Patent: May 22, 2018Assignee: Infineon Technologies Austria AGInventors: Peter Green, Hongying Ding, Roberto Quaglino
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Publication number: 20170310230Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.Type: ApplicationFiled: June 16, 2017Publication date: October 26, 2017Inventors: Roberto Quaglino, Giuseppe Bernacchia
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Patent number: 9716439Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.Type: GrantFiled: January 30, 2015Date of Patent: July 25, 2017Assignee: Infineon Technologies Austria AGInventors: Roberto Quaglino, Giuseppe Bernacchia
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Publication number: 20160226389Abstract: A power converter with an isolated topology may include a primary side and a secondary side. The secondary side includes a self-powered synchronous rectifier. The synchronous rectifier includes a synchronous rectifier transistor having at least a drain and a gate, a voltage regulator having at least an input that is coupled to the drain of the synchronous rectifier transistor, and an auxiliary transistor having at least a drain that is coupled to the drain of the synchronous rectifier transistor. The auxiliary transistor is on a same die as the synchronous rectifier transistor. The synchronous rectifier also includes a clamping device having at least an output that is coupled to the gate of the auxiliary transistor, and a gate driver circuit having at least: a power supply input that is coupled to the output of the voltage regulator, and an output that is coupled to a gate of the synchronous rectifier transistor.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: Roberto Quaglino, Giuseppe Bernacchia
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Patent number: 6822401Abstract: A method manages lamp fault conditions in electronic ballasts for one or more gas discharge lamps. The method for fault management of electronic ballast for at least one gas discharge lamp includes the steps of: preheating the lamp filaments applying a low current for a predetermined time; igniting the lamp by increasing at a predetermined rate the voltage applied up to a predetermined strike value; monitoring the lamp current; repeating the steps of igniting the lamp and monitoring the lamp current for a predetermined numbers of times if the lamp current is over a predetermined threshold; and powering the lamp at normal operating conditions.Type: GrantFiled: January 24, 2002Date of Patent: November 23, 2004Assignee: STMicroelectronics S.r.l.Inventors: Flavia Borella, Ugo Moriconi, Albino Pidutti, Roberto Quaglino, Francesca Sandrini
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Publication number: 20030006720Abstract: A method manages lamp fault conditions in electronic ballasts for one or more gas discharge lamps. The method for fault management of electronic ballast for at least one gas discharge lamp includes the steps of: preheating the lamp filaments applying a low current for a predetermined time; igniting the lamp by increasing at a predetermined rate the voltage applied up to a predetermined strike value; monitoring the lamp current; repeating the steps of igniting the lamp and monitoring the lamp current for a predetermined numbers of times if the lamp current is over a predetermined threshold; and powering the lamp at normal operating conditions.Type: ApplicationFiled: January 24, 2002Publication date: January 9, 2003Applicant: STMicroelectronics S.r.l.Inventors: Flavia Borella, Ugo Moriconi, Albino Pidutti, Roberto Quaglino, Francesca Sandrini
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Patent number: 6487059Abstract: The power supply device includes a DC-DC converter circuit having a power switch and a driving stage. The driving stage has a compensation terminal on which a compensation voltage is present, and which receives a biasing current. The driving stage includes a control circuit having an output terminal connected to a control terminal of the power switch and disconnection-detecting circuitry connected to the compensation terminal and generating a signal for permanent turning-off of the power switch when the biasing current drops below a current-threshold value. The driving stage moreover includes over-voltage detecting circuitry connected to the compensation terminal and generating a signal for temporary turning-off of the power switch when the compensation voltage exceeds a voltage-threshold value.Type: GrantFiled: July 30, 2001Date of Patent: November 26, 2002Assignee: STMicroelectronics S.r.l.Inventors: Gregorio Bontempo, Claudio Adragna, Mauro Fagnani, Albino Pidutti, Francesco Pulvirenti, Roberto Quaglino, Giuseppe Gattavari
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Publication number: 20020044463Abstract: The power supply device comprises a DC-DC converter circuit including a power switch and a driving stage. The driving stage has a compensation terminal on which a compensation voltage is present and which receives a biasing current, said driving stage comprising a control circuit having an output terminal connected to a control terminal of the power switch and disconnection-detecting means connected to said compensation terminal and generating a signal for permanent turning-off of said power switch when the biasing current drops below a current-threshold value. The driving stage moreover comprises over-voltage detecting means connected to the compensation terminal and generating a signal for temporary turning-off of said power switch when said compensation voltage exceeds a voltage-threshold value.Type: ApplicationFiled: July 30, 2001Publication date: April 18, 2002Applicant: STMicroelectronics S.r.l.Inventors: Gregorio Bontempo, Claudio Adragna, Mauro Fagnani, Albino Pidutti, Francesco Pulvirenti, Roberto Quaglino, Giuseppe Gattavari