Abstract: A medical telemetry system and method are provided for communication between an implantable medical device (IMD) and an external device (ExD). The method and system collects real-time (RT) data and non-real-time (NRT) data. The method and system segment the RT data into RT packets and the NRT data into NRT packets and load the RT and NRT packets into a shared transmit buffer in the IMD in accordance with RT and NRT bandwidth allocations and/or packet size. The method and system transmit the RT and NRT packets from the IMD to the ExD in an order loaded in the transmit buffer and adjust at least one of the RT and NRT bandwidth allocations and/or packet size based on a quality of service (QoS) characteristic.

Abstract: A process for forming memory quality silicon dioxide and silicon nitride dual-dielectric structures in the same LPCVD furnace system by: forming the silicon dioxide at atmospheric pressure at a temperature of 700.degree.-850.degree. using dry oxygen; heat treating the silicon dioxide layer in ammonia; and forming silicon nitride at 400-600 millitorr and 700.degree.-850.degree. C. using dichlorosilane and ammonia. Optionally, a dielectric layer of silicon oxynitride can be formed on the oxide by using N.sub.2 O, ammonia and dichlorosilane obtaining a memory device with improved retention and endurance.

Abstract: Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.

Abstract: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions. In the course of coplanar processing, the gate electrodes and S/D regions are defined. Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions. Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions. The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs. In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs. Thereafter, a second, silicon nitride layer of controlled thickness is deposited.