Patents by Inventor Roberto Sergio Matteo Maurino
Roberto Sergio Matteo Maurino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967972Abstract: Chopping techniques that suppress fold-back into the signal band and spreads the offset across the spectrum are described. By using various techniques, chopping may be performed with a variable frequency clock to spread the offset across the signal spectrum. Spreading the offset across the signal spectrum means that there are no longer large spurious tones at a few frequencies.Type: GrantFiled: May 3, 2022Date of Patent: April 23, 2024Assignee: Analog Devices International Unlimited CompanyInventors: Roberto Sergio Matteo Maurino, Bhargav R. Vyas, Ayesha Shaik
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Publication number: 20230421171Abstract: Techniques to deliver a precision low noise reference voltage to a precision analog-to-digital converter without the need of a reference buffer or digital correction. In an example, a technique can use an integrated resistor divider and external capacitor to derive a low noise precision reference voltage either from the power supply of the ADC, or from an integrated reference source.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Naiqian Ren, Roberto Sergio Matteo Maurino
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Publication number: 20230361784Abstract: Chopping techniques that suppress fold-back into the signal band and spreads the offset across the spectrum are described. By using various techniques, chopping may be performed with a variable frequency clock to spread the offset across the signal spectrum. Spreading the offset across the signal spectrum means that there are no longer large spurious tones at a few frequencies.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Roberto Sergio Matteo Maurino, Bhargav E. Vyas, Ayesha Shaik
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Publication number: 20230275592Abstract: Systems and techniques for Digital-to-Analog Converter (DAC) gain correction are described herein. A digital-to-analog converter (DAC) circuit can include a switch bridge circuit having a first leg and a second leg that define respective mutually exclusive first and second DAC signal paths. The DAC circuit can further include a first compensation circuit configured to provide a first compensation current to the first leg of the switch bridge to compensate for a current defect caused by a voltage drop across a portion of the first DAC signal path. The DAC circuit can also include a second compensation circuit configured to provide a. second compensation current to a second leg of the switch bridge to compensate for a voltage drop across a portion of the second DAC signal path. The DAC circuit can be included in a larger circuit such as a continuous time sigma delta (CTSD) analog-to-digital converter (ADC).Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Andrew Joseph Thomas, Roberto Sergio Matteo Maurino
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Patent number: 11545996Abstract: Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.Type: GrantFiled: August 24, 2021Date of Patent: January 3, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Roberto Sergio Matteo Maurino, Venkata Aruna Srikanth Nittala, Bhargav R. Vyas, Christopher Peter Hurrell, Andrew J. Thomas
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Patent number: 11251807Abstract: A wide bandwidth ADC circuit that combines a resistive-input continuous-time sigma-delta ADC circuit with a second ADC circuit having a switched capacitor input. The combination of these two ADC circuits can achieve an easy-to-drive, alias free, wide bandwidth ADC that has excellent DC precision.Type: GrantFiled: November 10, 2020Date of Patent: February 15, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Naiqian Ren, Roberto Sergio Matteo Maurino
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Patent number: 11190197Abstract: Noise sources in a pipelined ADC circuit can include kT/C sampling noise from a capacitor DAC circuit and residue amplifier sampling noise. The kT/C sampling noise is inversely proportional to the size of the sampling capacitors; the larger sampling capacitors produce less noise. However, larger sampling capacitor can be difficult to drive and physically occupy significant die area. By using the described techniques, the inversely proportional relationship between the sampling noise and the size of the sampling capacitors is no longer true. The size of the sampling capacitors can be greats reduced, which can reduce the die area and reduce the power consumption of the ADC, and the kT/C sampling noise can be canceled using correlated double sampling (CDS) techniques.Type: GrantFiled: February 19, 2019Date of Patent: November 30, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Sanjay Rajasekhar, Roberto Sergio Matteo Maurino
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Patent number: 11121718Abstract: Techniques to implement subtractive dither in a multi-stage ADC. Subtractive dither involves adding a first dither signal at a first node and adding a second dither signal at a second node (which can be the same as the first node), where the first and second dither signal combine and sum to approximately zero. By utilizing subtractive dither in a multi-stage ADC, the headroom requirements of a loop filter in a main loop of the ADC and the range requirements of a feedback DAC in the main loop can both be relaxed.Type: GrantFiled: August 12, 2020Date of Patent: September 14, 2021Assignee: Analog Devices International Unlimited CompanyInventor: Roberto Sergio Matteo Maurino
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Patent number: 10312926Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.Type: GrantFiled: June 20, 2018Date of Patent: June 4, 2019Assignee: Analog Devices Global Unlimited CompanyInventor: Roberto Sergio Matteo Maurino
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Publication number: 20190131989Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.Type: ApplicationFiled: June 20, 2018Publication date: May 2, 2019Inventor: Roberto Sergio Matteo Maurino
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Patent number: 10211788Abstract: A converter circuit is provided that includes an amplifier circuit and further includes: a summing current resistor that exhibits nonlinear resistance coupled between a voltage node and a summing current node of the amplifier; a compensation resistor circuit includes resistors that exhibit nonlinear resistance; the compensation resistor circuit produces a compensation current at the summing current node that compensates for nonlinear current flow in the summing current resistor.Type: GrantFiled: February 28, 2017Date of Patent: February 19, 2019Assignee: Analog Devices GlobalInventors: Roderick McLachlan, Roberto Sergio Matteo Maurino
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Patent number: 10128859Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.Type: GrantFiled: February 20, 2018Date of Patent: November 13, 2018Assignee: Analog Devices Global Unlimited CompanyInventors: Sanjay Rajasekhar, Roberto Sergio Matteo Maurino
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Publication number: 20180248527Abstract: A converter circuit is provided that includes an amplifier circuit and further includes: a summing current resistor that exhibits nonlinear resistance coupled between a voltage node and a summing current node of the amplifier; a compensation resistor circuit includes resistors that exhibit nonlinear resistance; the compensation resistor circuit produces a compensation current at the summing current node that compensates for nonlinear current flow in the summing current resistor.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Roderick McLachlan, Roberto Sergio Matteo Maurino
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Patent number: 9941897Abstract: A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.Type: GrantFiled: August 31, 2017Date of Patent: April 10, 2018Assignee: Analog Devices GlobalInventors: Hongxing Li, Roberto Sergio Matteo Maurino
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Patent number: 9893877Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.Type: GrantFiled: October 27, 2016Date of Patent: February 13, 2018Assignee: Analog Devices GlobalInventors: Mayur Gurunath Anvekar, Venkata Aruna Srikanth Nittala, Roberto Sergio Matteo Maurino, Naiqian Ren
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Patent number: 9800262Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.Type: GrantFiled: September 7, 2016Date of Patent: October 24, 2017Assignee: Analog Devices GlobalInventors: Roberto Sergio Matteo Maurino, Sanjay Rajasekhar, Pasquale Delizia, Colin G. Lyden, Gabriel Banarie
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Publication number: 20170207907Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.Type: ApplicationFiled: October 27, 2016Publication date: July 20, 2017Inventors: Mayur Gurunath Anvekar, Venkata Aruna Srikanth Nittala, Roberto Sergio Matteo Maurino, Naiqian Ren
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Patent number: 6903672Abstract: A signal processing component is provided where a swapper 702 is provided upstream of real and imaginary processing elements 704 and 706 within a system for processing complex signals. A further swapper 710 is provided downstream of the elements 704 and 706. The swappers 702 and 710 operate in unison.Type: GrantFiled: May 30, 2003Date of Patent: June 7, 2005Assignee: Analog Devices, Inc.Inventor: Roberto Sergio Matteo Maurino