Patents by Inventor Roberto Simola
Roberto Simola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299127Abstract: The integrated circuit comprises at least one transistor including a separate gate structure and field plate, disposed on a front face of a semiconductor substrate, and a doped conduction region in the semiconductor substrate located plumb with an edge of the gate structure and plumb with an edge of the field plate.Type: ApplicationFiled: March 7, 2023Publication date: September 21, 2023Applicant: STMicroelectronics (Rousset) SASInventors: Francois TAILLIET, Loic WELTER, Maria-Paz DUMITRESCU, Roberto SIMOLA
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Publication number: 20220367497Abstract: The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.Type: ApplicationFiled: May 2, 2022Publication date: November 17, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Francois TAILLIET, Roberto SIMOLA, Philippe BOIVIN
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Publication number: 20220139899Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.Type: ApplicationFiled: November 2, 2021Publication date: May 5, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Pascal FORNARA, Roberto SIMOLA
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Publication number: 20220140232Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.Type: ApplicationFiled: October 21, 2021Publication date: May 5, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Roberto SIMOLA, Yohann MOUSTAPHA-RABAULT
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Publication number: 20220123119Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Christian RIVERO, Philippe BOIVIN, Francois TAILLIET, Roberto SIMOLA
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Patent number: 11031082Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.Type: GrantFiled: May 5, 2020Date of Patent: June 8, 2021Assignee: STMicroelectronics (Rousset) SASInventors: Francois Tailliet, Roberto Simola
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Publication number: 20200265894Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Applicant: STMicroelectronics (Rousset) SASInventors: Francois TAILLIET, Roberto SIMOLA
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Patent number: 10679699Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.Type: GrantFiled: July 30, 2018Date of Patent: June 9, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Francois Tailliet, Roberto Simola
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Publication number: 20200035304Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.Type: ApplicationFiled: July 30, 2018Publication date: January 30, 2020Applicant: STMicroelectronics (Rousset) SASInventors: Francois TAILLIET, Roberto SIMOLA
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Patent number: 9954119Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.Type: GrantFiled: January 10, 2017Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Roberto Simola, Pascal Fornara
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Publication number: 20170148926Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.Type: ApplicationFiled: January 10, 2017Publication date: May 25, 2017Inventors: Roberto SIMOLA, Pascal FORNARA
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Patent number: 9577116Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.Type: GrantFiled: December 9, 2015Date of Patent: February 21, 2017Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Roberto Simola, Pascal Fornara
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Patent number: 9577053Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.Type: GrantFiled: December 9, 2015Date of Patent: February 21, 2017Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Roberto Simola, Pascal Fornara
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Publication number: 20160276496Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.Type: ApplicationFiled: December 9, 2015Publication date: September 22, 2016Inventors: Roberto Simola, Pascal Fornara
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Publication number: 20160276447Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.Type: ApplicationFiled: December 9, 2015Publication date: September 22, 2016Inventors: Roberto Simola, Pascal Fornara