Patents by Inventor Roberto Suaya
Roberto Suaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9230054Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: GrantFiled: December 8, 2014Date of Patent: January 5, 2016Assignee: Mentor Graphics CorporationInventor: Roberto Suaya
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Publication number: 20150161324Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: ApplicationFiled: December 8, 2014Publication date: June 11, 2015Applicant: Mentor Graphics CorporationInventor: Roberto Suaya
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Patent number: 8910108Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: GrantFiled: April 7, 2014Date of Patent: December 9, 2014Assignee: Mentor Graphics CorporationInventor: Roberto Suaya
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Patent number: 8826204Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: September 30, 2013Date of Patent: September 2, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Publication number: 20140223401Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventor: Roberto Suaya
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Patent number: 8732648Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: GrantFiled: June 15, 2012Date of Patent: May 20, 2014Assignee: Mentor Graphics CorporationInventor: Roberto Suaya
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Patent number: 8667446Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: March 29, 2010Date of Patent: March 4, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Patent number: 8650522Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: GrantFiled: April 16, 2012Date of Patent: February 11, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Publication number: 20140033164Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8549449Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: February 23, 2009Date of Patent: October 1, 2013Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8504962Abstract: Aspects of the invention relate to techniques for extracting admittance values associated with through-silicon vias in an integrated circuit system. A function fitting process is performed to generate parameters of a representation for electro-quasi-static potential Green's functions at a plurality of frequencies of interest based on integrated circuit manufacturing process information. Based on the generated parameters, a set of electric potential basis functions, a set of electric displacement basis functions and layout information for a layout design of interest, matrix elements of a matrix for each frequency in the plurality of frequencies of interest may be computed. The matrix is a part of a linear system that formulates a relationship of electric displacement fields and electric potentials in various regions associated with through-silicon vias in the layout design. Based on the matrix, admittance values associated with the through-silicon vias are computed.Type: GrantFiled: June 18, 2012Date of Patent: August 6, 2013Assignee: Mentor Graphics CorporationInventors: Vasileios Kourkoulos, Roberto Suaya
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Patent number: 8448115Abstract: Aspects of the invention relate to techniques for extracting impedance values associated with through-silicon vias in an integrated circuit system. A function fitting process is performed to generate parameters of a representation for magneto-quasi-static dyadic vector potential Green's functions at a plurality of frequencies of interest based on integrated circuit manufacturing process information. Based on the generated parameters, a set of electric current basis functions and the layout information for a layout design of interest, matrix elements of a matrix for each frequency in the plurality of frequencies of interest may be computed. The matrix is a part of a linear system that formulates a relationship of electric current and electric potential difference in various regions associated with the through-silicon vias in the layout design. Based on the matrix, impedance values associated with the through-silicon vias are computed.Type: GrantFiled: June 18, 2012Date of Patent: May 21, 2013Assignee: Mentor Graphics CorporationInventors: Vasileios Kourkoulos, Roberto Suaya
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Publication number: 20120254814Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: ApplicationFiled: June 15, 2012Publication date: October 4, 2012Inventor: Roberto Suaya
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Publication number: 20120204139Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Inventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Patent number: 8225266Abstract: Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrands for calculating the matrix elements into simplified terms that are less computationally intensive than the integrands and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media).Type: GrantFiled: September 19, 2011Date of Patent: July 17, 2012Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Salvador Ortiz
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Patent number: 8214788Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.Type: GrantFiled: March 9, 2009Date of Patent: July 3, 2012Assignee: Mentor Graphics CorporationInventor: Roberto Suaya
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Patent number: 8161438Abstract: Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.Type: GrantFiled: May 16, 2006Date of Patent: April 17, 2012Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Salvador Ortiz
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Publication number: 20120011485Abstract: Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrands for calculating the matrix elements into simplified terms that are less computationally intensive than the integrands and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media).Type: ApplicationFiled: September 19, 2011Publication date: January 12, 2012Inventors: Roberto Suaya, Salvador Ortiz
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Patent number: 8091054Abstract: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.Type: GrantFiled: September 15, 2008Date of Patent: January 3, 2012Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar
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Patent number: 8024692Abstract: Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired frequency of operation for the circuit design is received. Conduction modes representing distribution functions for currents in the conductors at the desired frequency of operation are defined. A conduction mode matrix including matrix elements based on the defined conduction modes is generated. Values for one or more matrix elements are computed by decomposing integrands for calculating the matrix elements into simplified terms that are less computationally intensive than the integrands and computing the values of the simplified terms. The values for the one or more matrix elements can be stored (e.g., on one or more computer-readable media).Type: GrantFiled: May 2, 2008Date of Patent: September 20, 2011Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Salvador Ortiz