Abstract: A signal processor includes at least one data source (3), a plurality of input registers (11, 12, 13, 14, . . . ) whose inputs are coupled to the data source by data buses (9, 10), a plurality of multipliers (19, 20; 71, 72 . . . ) for multiplying data buffered in the input registers, and a processing arrangement spread over a plurality of data processor branches (4-0, 4-1, . . . , 4-N) for processing products (p0, p1, . . . ), generated by the multipliers by arithmetic and/or logic operations. For achieving enhanced flexibility of the signal processor and increasing the number of possible applications, multiplexers (15, 16, 17, 18; 70) are provided which are used for coupling the multipliers to a respective part of the input registers in dependence on control signals (I, II, III, IV). Such a signal processor is preferably used in mobile radio technology. Further fields of application are, for example, audio, video, medical and automotive technology, ISDN systems, and digital radio.

Abstract: The invention relates to a data processing system, having a number of data processing units and a program memory for instruction words, each of which has separate command fields for the various data processing units so that the data processing units can be independently controlled by means of a program. The data terminals of the data processing units are interconnected via various buses. The connections established by the buses are controlled, via an expander, by way of a control field in the instruction word. The expander provides a limited repertory of feasible connections, selected in dependence on the type of program.

Abstract: A one-dimension transformer for use in Transform Picture Coding converts each of a series of N input words into a series of N product words by multiplying this series and a transform matrix of N.times.N transform elements. This transformer has a main input connection bus (14.22) which receives the series of input words, a main output connection bus (14.29) at which the desired N product words occur successively and furthermore three data connection buses (14.23; 14.24; 14.25). For performing the required mathematical operations three circuits are provided; two combination circuits (14.30 and 14.31) for adding or subtracting data words applied thereto to generate result words at their outputs and a multiplier circuit 14.32 for multiplying a data word applied thereto by a mulitplication factor which is related to the transform elements to generate an auxiliary product word at its output. The associated output of each of these three circuits is connected to a different one of the three data connection buses.

Abstract: A very large scale integrated circuit comprises a number of function blocks which are synchronized by relevant clock signals. Each function block forms an isochronous region so that the delay times of the signals within the relevant function block can be negligibly small with respect to the gate delay times. Each function block is paired with at least one other function block in that the pair is connected by an information connection and by at least two synchronization handshake lines for transporting synchronization signals dispatched by each function block of the pair to the other function block of the pair so that an asynchronous information transport is obtained. One or more of the function blocks comprises an information connection to the environment. As a result of this set-up, the circuit can also be tested and designed per function block.