Abstract: An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Abstract: An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Abstract: An encoder/decoder architecture for buses, capable of minimizing power consumption by reducing the switching activity, generates, from an input information value relating to a given instant, a corresponding current output value on encoded bus lines relating to the same given instant. The architecture including storage device for storing respective preceding values of input information and output information relating to instants preceding the aforesaid given instant. A prediction block generates, from the preceding value of input information, an estimate of the current input information value. A decorrelation block decorrelates the current input information value with respect to the said estimate. A selection block selects as the current output value one out of the current input information value, the result of the decorrelation implemented by the decorrelation block or the preceding output value.

Abstract: A method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks is discussed. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.