Abstract: The invention relates to an integrated circuit comprising a substrate having a first side and a second opposing side. An electronic circuit (EC) is provided at the first side (S1) of the substrate, wherein the electronic circuit (EC) comprises at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit further comprises a magnetizable region (MR) provided on the second side (S1) of the substrate (SUB) by using a wafer-level type deposition processing step. The magnetic moment of the magnetizable region (MR) is configurable for generating a magnetic field (H1, H2) detectable at the location of the at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit constitutes a very simple construction and enables a strongly miniaturized solution which is, because of its reduced dimensions well suitable for being used in bank cards. An attempt to remove the integrated circuit according to the invention from its environment (e.g.

Abstract: A phase change memory cell, e.g. a line-cell (2), and fabrication thereof, the cell comprising: two electrodes (6, 8); phase change memory material (10) and a dielectric barrier (12). The dielectric barrier (12) is arranged to provide electron tunnelling, e.g. Fowler-Nordheim tunnelling, to the phase change memory material (10). A contact (15) made of phase change memory material may also be provided. The dielectric barrier (12) is substantially uniform e.g. of substantially uniform thickness, e.g. ?5 nm.

Abstract: The invention relates to a tamper-resistant semiconductor device comprising a substrate (5) comprising an electronic circuit arranged on a first side thereof. An electrically-conductive protection layer (50, 50a, 50b) is arranged on a second side of the substrate (5) opposite to the first side. At least three through-substrate electrically-conductive connections (45) extend from the first side of the substrate (5) into the substrate (5) and in electrical contact with the electrically-conductive protection layer (50, 50a, 50b) on the second side of the substrate (5). A security circuit is arranged on the first side connected to the through-substrate electrically-conductive connections (45) and is arranged for measuring at least two resistance values (R12, R23, R34, R14, R13, R24) of the electrically-conductive protection layer (50, 50a, 50b) through the through-substrate electrically-conductive connections (45).

Abstract: An integrated circuit has an inhomogeneous protective layer or coating over a circuit to be protected, and a sensing circuit (80) arranged to sense a first impedance of a part of the protective coating compared to a reference impedance (CO) located on the integrated circuit. The sensing circuit is able to measure a change in the first impedance, e.g. caused by tampering. The sensing circuit has an amplifier (OTA) having a feedback loop, such that the impedance being sensed is in the feedback loop. The sensing circuit can be incorporated in an oscillator circuit (OTA, Comp) so that the frequency depends on the impedance. Where the impedance is a capacitance, sensing electrodes adjacent to the protective layer or coating, form the capacitance. The electrodes can be arranged as selectable interdigitated comb structures, so that the protective layer or coating extends in between the teeth of the comb structures.

Abstract: A phase change memory cell, e.g. a line-cell (2), and fabrication thereof, the cell comprising: two electrodes (6, 8); phase change memory material (10) and a dielectric barrier (12). The dielectric barrier (12) is arranged to provide electron tunnelling, e.g. Fowler-Nordheim tunnelling, to the phase change memory material (10). A contact (15) made of phase change memory material may also be provided. The dielectric barrier (12) is substantially uniform e.g. of substantially uniform thickness, e.g. ?5 nm.

Abstract: A damascene process is described using a copper fill process to fill a trench (12). The copper fill (20) is started with a deposited seed layer which includes (5) copper and titanium. Some titanium migrates to the surface during the copper fill process. The structure is annealed in a nitrogen atmosphere which creates a self-aligned TiN barrier (24) at the surface of the copper fill (20). Air gaps (26) may be created in the same annealing process. The process may be used to form a multilayer structure.

Abstract: The invention relates to an integrated circuit comprising a substrate having a first side and a second opposing side. An electronic circuit (EC) is provided at the first side (S1) of the substrate, wherein the electronic circuit (EC) comprises at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit further comprises a magnetizable region (MR) provided on the second side (S1) of the substrate (SUB) by using a wafer-level type deposition processing step. The magnetic moment of the magnetizable region (MR) is configurable for generating a magnetic field (H1, H2) detectable at the location of the at least one magnetic field sensor Snsr3 (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit constitutes a very simple construction and enables a strongly miniaturized solution which is, because of its reduced dimensions well suitable for being used in bank cards. An attempt to remove the integrated circuit according to the invention from its environment (e.g.

Abstract: The present invention relates to particles comprising a core and a shell, a method of producing said particle, various uses of said particle as well as various products comprising said particle. The particle according to the invention may be used as photocatalyst, as antibacterial agent, as cleaning agent, as anti-fogging agent and as decomposing agent. Furthermore the particle is applicable as solar cells.

Abstract: The invention relates to a tamper-resistant semiconductor device comprising a substrate (5) comprising an electronic circuit arranged on a first side thereof. An electrically-conductive protection layer (50, 50a, 50b) is arranged on a second side of the substrate (5) opposite to the first side. At least three through-substrate electrically-conductive connections (45) extend from the first side of the substrate (5) into the substrate (5) and in electrical contact with the electrically-conductive protection layer (50, 50a, 50b) on the second side of the substrate (5). A security circuit is arranged on the first side connected to the through-substrate electrically-conductive connections (45) and is arranged for measuring at least two resistance values (R12, R23, R34, R14, R13, R24) of the electrically-conductive protection layer (50, 50a, 50b) through the through-substrate electrically-conductive connections (45).

Abstract: An integrated circuit has an inhomogeneous protective layer or coating over a circuit to be protected, and a sensing circuit (80) arranged to sense a first impedance of a part of the protective coating compared to a reference impedance (CO) located on the integrated circuit. The sensing circuit is able to measure a change in the first impedance, e.g. caused by tampering. The sensing circuit has an amplifier (OTA) having a feedback loop, such that the impedance being sensed is in the feedback loop. The sensing circuit can be incorporated in an oscillator circuit (OTA, Comp) so that the frequency depends on the impedance. Where the impedance is a capacitance, sensing electrodes adjacent to the protective layer or coating, form the capacitance. The electrodes can be arranged as selectable interdigitated comb structures, so that the protective layer or coating extends in between the teeth of the comb structures.

Abstract: A damascene process is described using a copper fill process to fill a trench (12). The copper fill (20) is started with a deposited seed layer which includes (5) copper and titanium. Some titanium migrates to the surface during the copper fill process. The structure is annealed in a nitrogen atmosphere which creates a self-aligned TiN barrier (24) at the surface of the copper fill (20). Air gaps (26) may be created in the same annealing process. The process may be used to form a multilayer structure.

Abstract: In the method a first layer, particularly of amorphous silicon, is deposited on the surface of a substrate with trenches. Part of this surface is covered with a protective layer. The first layer is thereafter maskless removed with a dry etching treatment on the substrate surface while it is kept within the trench.

Abstract: A phase change resistor device has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. For ease of manufacturing the PCM is an elongate line structure (210, 215) surrounded by the conductive electrode portions (200, 240) at its lateral sides, and is formed in a CMOS backend process. An alternative is to form the device coupled directly to other circuit parts without the electrodes. In each case, there is a line of PCM which has a constant diameter or cross section, formed with reduced dimensions by using a spacer as a hard mask. The first contact electrode and the second contact electrode are electrically connected by a “one dimensional” layer of the PCM. The contact resistance between the one-dimensional layer of PCM and the first contact electrode at the second contact electrode is lower than the resistance of a central or intervening portion of the line.

Abstract: The invention relates to a semiconductor device comprising a semiconductor body (3) with a semiconductor element (1) with an electrically conducting region (5) on which a capacitor (2) forming a memory element is present with a lower electrode (11), an oxidic ferroelectric dielectric (12), and an upper electrode (13), which lower electrode (11) makes electrical contact with the conducting region (5) and comprises a layer with a conductive metal oxide (112) and a layer (111) comprising platinum. The layer with the conductive metal oxide (112) acts as an oxygen barrier during manufacture. The invention also relates to a method of manufacturing such a semiconductor device.According to the invention, the device is characterized in that the layer comprising platinum (111) contains more than 15 atom % of a metal capable of forming a conductive metal oxide, and in that the layer (112) with the conductive metal oxide is present between the layer (111) comprising platinum and the ferroelectric dielectric (12).

Abstract: A method of manufacturing semiconductor devices whereby first a Ti layer (8) and then a TiN layer (9) are deposited on slices of semiconductor material (20). The slices are placed on a support (30) one after the other in a deposition chamber (22), the support being positioned opposite a target of Ti (32) surrounded by an annular anode (31). Material is then sputtered off the target by means of a plasma (35) generated near the target. The plasma is generated in Ar during deposition of the Ti layer and in a gas mixture of Ar and N.sub.2 during deposition of the TiN layer. After the deposition of the TiN layer, before a next slice is placed in the chamber each time, the target is cleaned during an additional process step in that material is sputtered off the target by means of a plasma generated in Ar. The additional process step is ended the moment the target has regained a clean Ti surface again.

Abstract: A semiconductor device includes a semiconductor body (3) with a semiconductor element (1) with an electrically conducting region (5) on which a capacitor (2) forming a memory element is present with a lower electrode (11), an oxidic ferroelectric dielectric (12), and an upper electrode (13), which lower electrode (11) makes electrical contact with the conducting region (5) and includes a layer with a conductive metal oxide (112) and a layer (111) including platinum. The layer with the conductive metal oxide (112) acts as an oxygen barrier during manufacture. The invention also relates to a method of manufacturing such a semiconductor device. The device is characterized in that the layer including platinum (111) contains more than 15 atom % of a metal capable of forming a conductive metal oxide, and in that the layer (112) with the conductive metal oxide is present between the layer (111) comprising platinum and the ferroelectric dielectric (12).

Abstract: A semiconductor device in which a capacitor (2) is provided on a surface (10) of a semiconductor body (3) with a semiconductor element (1) in which a lower electrode (11), an oxidic ferroelectric dielectric (12) and an upper electrode (13) are provided in that order, the upper electrode not covering an edge of the dielectric, after which an insulating layer (14) with superimposed metal conductor tracks is provided. According to the invention, the edge of the dielectric (12) not covered by the upper electrode (13) is coated with a coating layer (14, 20, or 30) practically imperviable to hydrogen, after which the device is heated in a hydrogen-containing atmosphere. Heating in a hydrogen atmosphere neutralizes dangling bonds which arise during deposition of the conductor tracks on the insulating layer, while the coating layer protects the dielectric from attacks by hydrogen. The semiconductor device then has a shorter access time.

Abstract: A method of manufacturing a semiconductor device whereby on a surface (1) of a semiconductor body (2) a layer comprising aluminum (3) is deposited, in which conductor tracks (4) are etched, between which then an insulating aluminum compound (6) is provided in that a layer of such a material (7) is deposited, which layer is then removed down to the conductor tracks (4) by a bulk reducing treatment, upon which an insulating layer (11) is deposited into which contact windows (13, 14) are etched down to the layer comprising aluminum (4) for local contacting of the conductor tracks (4). The conductor tracks (4) are provided with a top layer (8) before the deposition of the insulating aluminum compound, and the aluminum compound is removed again down to the top layer (8) after the deposition by means of a polishing treatment which is practically incapable of removing the top layer (8).

Abstract: A semiconductor device in which a capacitor (2) is provided on a surface (10) of a semiconductor body (3) with a semiconductor element (1) in which a lower electrode (11), an oxidic ferroelectric dielectric (12) and an upper electrode (13) are provided in that order, the upper electrode not covering an edge of the dielectric, after which an insulating layer (14) with superimposed metal conductor tracks is provided. According to the invention, the edge of the dielectric (12) not covered by the upper electrode (13) is coated with a coating layer (14, 20, or 30) practically imperviable to hydrogen, after which the device is heated in a hydrogen-containing atmosphere. Heating in a hydrogen atmosphere neutralizes dangling bonds which arise during deposition of the conductor tracks on the insulating layer, while the coating layer protects the dielectric from attacks by hydrogen. The semiconductor device then has a shorter access time.

Abstract: A method of manufacturing a semiconductor device is set forth comprising a semiconductor body (1) having a surface (2) adjoined by a semiconductor region (3) and a field oxide region (4) surrounding this region, on which surface (2) is provided a metal layer (13), in which a conductor track (17, 18) is formed, after which an isolating layer of silicon oxide (19) is deposited over the conductor track (17, 18) on the surface (2). According to the invention, before the layer of silicon oxide (19) is provided over the conductor track (17, 18), this track is provided with a top layer (16) of an oxidation-preventing material. By providing this top layer (16), it is avoided that the conductor track (17, 18) covered by silicon oxide (19) has a high electrical resistance or even an electrical interruption.