Abstract: Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion; a passivation stack covering the metallization stack; and a sensor including a sensing material on the passivation stack, said sensor being coupled to the first metal portion by a via extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

Abstract: The method of manufacturing a solar cell comprises the steps of: (a) providing the semiconductor substrate in a deposition chamber of a vapour deposition apparatus, which semiconductor substrate comprises a passivation layer at a first side thereof which passivation layer is patterned to define contact areas at which the copper-containing conductor is present; (b) supplying a gaseous silicon species into the deposition chamber, resulting in the formation of a surface layer of a copper silicide on a surface of the copper-containing conductor and in the formation of amorphous silicon on top of the passivation layer, and (c) providing a protective layer of an insulating silicon compound on the surface layer, wherein the protective cover comprising both the surface layer and the protective layer.

Abstract: Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion; a passivation stack covering the metallization stack; and a sensor including a sensing material on the passivation stack, said sensor being coupled to the first metal portion by a via extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion (20); a passivation stack (24, 26, 28) covering the metallization stack; and a sensor including a sensing material (40) on the passivation stack, said sensor being coupled to the first metal portion by a via (34) extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

Abstract: The method of manufacturing a solar cell, comprising the steps of providing a solar cell device comprising a semiconductor body (10) and having a first side (11) and an opposed second side (12), which first side is intended for capturing incident light and which second side is intended for assembly to a carrier, which solar cell device comprises a first contact region (13) in the semiconductor body (10) at one of the first (11) and the second side (12); applying an optically transparent structure (22) of electrically insulating material to at least one of the sides (11, 12) of the solar cell device, which structure is patterned to form an aperture to the first contact region (13); providing a contact structure (41, 42, 43) of electrically conducting material in said aperture by means of electrochemical deposition.

Abstract: The method of manufacturing a solar cell comprises the steps of: (a) providing the semiconductor substrate in a deposition chamber of a vapour deposition apparatus, which semiconductor substrate comprises a passivation layer at a first side thereof which passivation layer is patterned to define contact areas at which the copper-containing conductor is present; (b) supplying a gaseous silicon species into the deposition chamber, resulting in the formation of a surface layer of a copper silicide on a surface of the copper-containing conductor and in the formation of amorphous silicon on top of the passivation layer, and (c) providing a protective layer of an insulating silicon compound on the surface layer, wherein the protective cover comprising both the surface layer and the protective layer.

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: The invention relates to a method for proving authenticity of a prover PRV to a verifier VER, the method comprising generating a secret S using a physical token by the prover PRV. Obtaining a public value PV by the verifier, where the public value PV has been derived from the secret S using a function for which the inverse of said function is computationally expensive. The method further comprising a step for conducting a zero knowledge protocol between the prover PRV and the verifier VER in order to prove to the verifier VER, with a pre-determined probability, that the prover PRV has access to the physical token, where the prover PRV makes use of the secret S and the verifier VER makes use of the public value PV. The invention further relates to a system employing the method, and an object for proving authenticity.

Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.

Abstract: An MR sensor arrangement is integrated with an IC. A metal layer of the IC structure (e.g. CMOS) is patterned to define at least first and second contact regions. Metal connecting plugs are provided below the first and second contact regions of the metal layer for making contact to terminals of the integrated circuit. A magnetoresistive material layer is above the metal layer and separated by a dielectric layer. Second metal connecting plugs extend up from the metal layer to an MR sensor layer. The sensor layer is thus formed over the top of the layers of the IC structure.

Abstract: A method of manufacturing a Bulk Acoustic Wave device by providing an active layer formed of an electro-mechanical transducer material, providing a first electrode on the active layer, defining a first electrode portion of the device, whereby a remaining portion of the device is defined around the first electrode, providing a stop-layer on the first electrode, depositing a first dielectric layer on the resultant structure, and planarizing the first dielectric layer until the stop-layer on the first electrode is exposed.

Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion (20); a passivation stack (24, 26, 28) covering the metallization stack; and a sensor including a sensing material (40) on the passivation stack, said sensor being coupled to the first metal portion by a via (34) extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

Abstract: The electric device according to the invention has a resistor comprising a layer of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device further comprises a switching signal generator for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer of the phase change material from the first phase to the second phase.

Abstract: A method of manufacturing a Bulk Acoustic Wave device by providing an active layer formed of an electro-mechanical transducer material, providing a first electrode on the active layer, defining a first electrode portion of the device, whereby a remaining portion of the device is defined around the first electrode, providing a stop-layer on the first electrode, depositing a first dielectric layer on the resultant structure, and planarizing the first dielectric layer until the stop-layer on the first electrode is exposed.

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: An MR sensor arrangement is integrated with an IC. A metal layer of the IC structure (e.g. CMOS) is patterned to define at least first and second contact regions. Metal connecting plugs are provided below the first and second contact regions of the metal layer for making contact to terminals of the integrated circuit. A magnetoresistive material layer is above the metal layer and separated by a dielectric layer. Second metal connecting plugs extend up from the metal layer to an MR sensor layer. The sensor layer is thus formed over the top of the layers of the IC structure.

Abstract: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.

Abstract: The semiconductor device of the invention includes a circuit and a protecting structure. It is provided with a first and a second security element and with an input and an output. The security elements have a first and a second impedance, respectively, which impedances differ. The device is further provided with a measuring unit a processing unit and a connection unit. The processing unit transform any first information received into a specific program of measurement. Herewith a challenge-response mechanism is implemented in the device.

Abstract: The semiconductor device (11) of the invention comprises a circuit covered by a passivation structure (50). It is provided with a first and a second security element (12A, 12B) which comprise local areas of the passivation structure (50), and with a first and a second electrode (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which impedances differ. This is realized in that the passivation structure has an effective dielectric constant that varies laterally over the circuit. Actual values of the impedances are measured by measuring means and transferred to an access device by transferring means. The access device comprises or has access to a central database device for storing the impedances. The access device furthermore may compare the actual values with the stored values of the impedances in order to check the authenticity or the identity of the semiconductor device.

Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.