Patents by Inventor Robertus M. W. Raaijmakers

Robertus M. W. Raaijmakers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit with interconnect test unit
    Patent number: 6807505
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: October 19, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Franciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg
  • Circuit with interconnect test unit
    Publication number: 20040059535
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Application
    Filed: July 16, 2003
    Publication date: March 25, 2004
    Inventors: Franciscus G.M. De Jong, Mathias N.M. Muris, Robertus M.W. Raaijmakers, Guillaume E.A. Lousberg
  • Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit
    Patent number: 6622108
    Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: September 16, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Franciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg