Patents by Inventor Robertus Theodorus Franciscus Van Schaijk

Robertus Theodorus Franciscus Van Schaijk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090200536
    Abstract: The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
    Type: Application
    Filed: June 28, 2005
    Publication date: August 13, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Robertus Theodorus Franciscus Van Schaijk, Prabhat Agarwal, Erik Petrus Antonius Maria Bakkers, Martijn Henri Richard Lankhorst, Michiel Jos Van Duuren, Abraham Rudolf Balkenende, Louis Felix Feiner, Pierre Hermanus Woerlee
  • Publication number: 20090179254
    Abstract: Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the ma
    Type: Application
    Filed: September 13, 2006
    Publication date: July 16, 2009
    Applicant: NXP B.V.
    Inventors: Robertus Theodorus Franciscus Van Schaijk, Pablo Garcia Tello, Michiel Slotboom