Abstract: The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.

Abstract: Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising: —providing the substrate having the first semiconductor layer; —depositing the charge trapping layer; —depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and —creating a shallow trench isolation in between said at least two non-volatile memory cells.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising:—providing the substrate having the first semiconductor layer;—depositing the charge trapping layer;—depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and—creating a shallow trench isolation in between said at least two non-volatile memory cells.

Abstract: The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of the present invention does not require mask alignment sensitivity and makes it possible to implant self-aligned an extended drain for erasing of the memory device. Furthermore, the method provides a way of performing separately drain and source implant with different doping without the use of an additional mask.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: A non-volatile memory device (1, 101, 201, 301) having a gap within a tunnel dielectric layer (14, 114, 214, 314) and a method of manufacturing the same is provided. The devices have a stack of layers on top of a substrate (10, 110, 210, 310) including, a charge tunneling layer with a gap (14, 114, 214, 314), a charge storage layer (16, 116, 216, 316), a control gate layer (20, 120, 220, 320) and an insulating layer (18, 118, 218 220) in between the charge storage layer and the control gate. Manufacturing proceeds through deposition of a sacrificial layer (28, 128,228,328) on parts of a substrate, whereupon a stack of layers (24, 124,224,324) including a charge-storage layer, an insulating layer and a control gate layer are formed. Subsequently, selected parts of the sacrificial layer are removed, thereby forming a gap in between the charge storage region and the substrate. The gap is protected from future processing by deposition of a sealing layer (34, 134, 234, 334).

Abstract: The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (10), each device having a floating gate (36), comprising: first forming isolation zones (14) in the substrate (10), thereafter forming a floating gate separator (32) on the isolation zones (14) at locations where separations between adjacent floating gates (36) are to be formed, after forming the floating gate separator (32), forming the floating gates (36) on the substrate (10) between parts of the floating gate separator (32), and thereafter removing the floating gate separator (32) so as to obtain slits in between neighboring floating gates (36). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur.

Abstract: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9).

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: A method to improve the coupling ratio between a control gate (18) and a floating gate (14) of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer (24) is used at both sides of the stack. The conductive spacer (24) is galvanically connected to the control gate (18), preferably by means of a conductive layer (34), whereas it is separated from the floating gate (14) by means of an insulating layer (22). The capacitance (C1, C2) between both conductive spacers (24) and the side walls of the floating gate (14) adds up to the normal capacitance between control gate (18) and floating gate (14).

Abstract: A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions (4) which are mutually isolated by field-oxide regions (3 of 4). On the surface (2) a first system of conductors 11 is then formed which are directed perpendicularly to the active regions and are covered by an insulating layer (12), charge storage regions (13) being formed below these conductors, at the location where these conductors and the active regions cross each other. These conductors form word lines of the memory and, at the location where said conductors and the active regions cross each other, they form control gates. Next, a conductive layer (16) is deposited and planarized. The planarized conductive layer (16) is then provided with an etch mask with strips directed perpendicularly to the active regions, which strips extend above and next to the conductors (11).

Abstract: Consistent with an example embodiment, there is a method for manufacturing a semiconductor device. The semiconductor device comprises a semiconductor body provided at a surface with a non-volatile memory including a memory cell with a gate structure with an access gate and a gate structure with a control gate and a charge storage region situated between the control gate and the semiconductor body. In the method, on the surface of the semiconductor body a first one of said gate structures is formed with side walls extending substantially perpendicular to the surface, a conductive layer is deposited on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining only a first one of the side walls of the first gate structure.