Abstract: The present invention provides a method of manufacturing on a substrate (50) a 2-transistor memory cell comprising a storage transistor (1) having a memory gate stack (1) and a selecting transistor, there being a tunnel dielectric layer (51) between the substrate (50) and the memory gate stack. (1). The method comprises forming the memory gate stack (1) by providing a first conductive layer (52) and a second conductive layer (54) and etching the second conductive layer (54) thus forming a control gate and etching the first conductive layer (52) thus forming a floating gate. The method is characterized in that it comprises, before etching the first conductive layer (52), forming spacers (81) against the control gate in the direction of a channel to be formed under the tunnel dielectric layer (51), and thereafter using the spacers (81) as a hard mask to etch the first conductive layer (52) thus forming the floating gate, thus making the floating gate self aligned with the control gate.

Abstract: Semiconductor device comprising a vertical split gate non-volatile memory cell, for storing at least one bit, on a semiconductor substrate, comprising on the substrate a trench, a first active area, a second active area, a channel region extending along a sidewall of the trench, the trench having a length extending in a first direction and a width extending in a second direction perpendicular thereto and the trench being covered on the sidewalls by a tunnel oxide and including at least one gate stack of a floating gate and a control gate, wherein the control gate extends to the bottom part of the trench, a first floating gate is located at a left trench wall to form a first stack with the control gate, and a second floating gate is located at a right trench wall to form a second stack with the control gate.

Abstract: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9).

Abstract: The present invention describes an array structure (10) for non-volatile semiconductor memory elements (14, 16) with a high area density. This high density is obtained by the combination of a commonly used virtual ground scheme and a 2-dimensional array of memory elements (14, 16). Wordlines (18, 20) connecting memory elements (14, 16) in a row or a column cross each other at insulated cross-points (22). Furthermore, the invention describes a possible fabrication process for such memory arrays.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: A method to improve the coupling ratio between a control gate (18) and a floating gate (14) of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer (24) is used at both sides of the stack. The conductive spacer (24) is galvanically connected to the control gate (18), preferably by means of a conductive layer (34), whereas it is separated from the floating gate (14) by means of an insulating layer (22). The capacitance (C1, C2) between both conductive spacers (24) and the side walls of the floating gate (14) adds up to the normal capacitance between control gate (18) and floating gate (14).

Abstract: A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions (4) which are mutually isolated by field-oxide regions (3 of 4). On the surface (2) a first system of conductors 11 is then formed which are directed perpendicularly to the active regions and are covered by an insulating layer (12), charge storage regions (13) being formed below these conductors, at the location where these conductors and the active regions cross each other. These conductors form word lines of the memory and, at the location where said conductors and the active regions cross each other, they form control gates. Next, a conductive layer (16) is deposited and planarized. The planarized conductive layer (16) is then provided with an etch mask with strips directed perpendicularly to the active regions, which strips extend above and next to the conductors (11).