Abstract: A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be other than three. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.

Abstract: A method is described, in which a self-test is controlled in a subsystem of a data processing system. Control patterns are transported by the data processing system via a shift register and are then passed to the subsystem via connections used for normal control in the non-testing condition. A characterization of the test result is then loaded again into the shift register via connections also intended for normal use and is subsequently transported by the data processing system. A subsystem suitable for a self-test according to this method is controllable in the self-test condition from a shift register without it being necessary that it is provided with special test connections.

Abstract: A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes:a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function,b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle,c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.