Abstract: A method of optimizing a three-dimensional component layout in accordance with predetermined constraints is comprised of the steps of generating a plurality of models for each component. The plurality of models is arranged in a hierarchy from the model having the least resolution to the model having the most resolution. A starting layout is selected for the components. An iterative type of optimization routine is performed wherein each iteration is evaluated for satisfaction of the constraints using models for the components selected according to the level of resolution desired at that time in the iterative process. The optimization routine ends when a predetermined ending criterion is met.

Abstract: Serial neighborhood image processing stages, preferably arranged in a pipeline, are used to layout conductor paths on circuits such as printed circuit boards and integrated circuit devices. Pixels associated with areas on the circuit corresponding with source, target, free and blocked cells are encoded with preselected pixel values. The circuit image is then transmitted to the neighborhood transformation stages in a raster scan line format. The stages analyze the pixel values in each neighborhood and transform free cells into digital representations of conductor paths between the source and target.