Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing, wherein the first housing electrode 5 comprises an electrode plate; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes by pressure; a thermal coupler 17 arranged within the housing between the plurality of semiconductor units 30 and the electrode plate of the first housing electrode 5; a first array of pillars 10 extending between the plurality of semiconductor units 30 and the thermal coupler 17, and electrically coupled to the plurality of semiconductor units 30, respectively; and a second array of pillars 18 extending between the thermal coupler 17 and the electrode plate of the first housing electrode 5, wherein the first array of pillars 10 are electrically coupled to the elec

Abstract: A semiconductor device comprising: a plurality of semiconductor chips; a first conductor and a second conductor arranged at opposite sides of the semiconductor chips, wherein the second conductor comprises a plurality of pillars, and wherein each of the semiconductor chips comprises: a first surface facing the first conductor; a first electrode arranged on the first surface and electrically coupled to the first conductor; a second surface opposite to the first surface; a second electrode arranged on the second surface and electrically coupled to a respective one of the pillars, and a control electrode arranged on the second surface and configured to switch a current flowing between the first electrode and the second electrode; a circuit board comprising openings penetrated by the plurality of pillars, wherein the circuit board further comprises an electrically insulating layer, a first conductive film and a second conductive film.

Abstract: There is provided a semiconductor device 1 which comprises: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing; a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5; a plurality of pressure means 40 for applying pressure to the plurality of semiconductor units 30, respectively, wherein the plurality of pressure means 40 are arranged between the plurality of semiconductor units 30 and the first housing electrode 5; a first conductive structure 14 arranged between the plurality of pressure means 40 and the plurality of semiconductor units 30, wherein the plurality of semiconductor units 30 are electrically connected in parallel between the second housing electrode 4 and the first conductive structure 14; and a second conductive structure 18 configured to provide a current flow path from the first conductive structure 14 to the first housing electrode 5, the second

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising: a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing, and a tubular housing element 8 arranged between the first and second housing electrodes 4, 5 and configured to electrically isolate the first and second housing electrodes 4, 5 from one another; at least one semiconductor chip 20 arranged within the housing between the first and second housing electrodes 4, 5; and a metal explosion shield 12 arranged within the housing, wherein the metal explosion shield 12 is configured to extend into a space formed between the at least one semiconductor chip 20 and the tubular housing element 8 such that the metal explosion shield surrounds the at least one semiconductor chip 20.

Abstract: The present disclosure provides a semiconductor device 1, comprising: a housing comprising an internal space; at least one semiconductor chip 20 arranged inside the housing; and a separator 13 arranged inside the housing and configured to separate the internal space of the housing into a first chamber 11 and a second chamber 12, wherein the at least one semiconductor chip 20 is arranged within the first chamber 11; wherein the separator 13 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between the first and second chambers 11, 12 exceeds a threshold differential pressure or a temperature at the deformable portion 15 exceeds a threshold temperature, so as to transform the first chamber 11 from a hermetically sealed chamber to an open chamber in fluid communication with the second chamber 12.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a housing electrode 4; and at least one semiconductor chip 20 arranged within the housing; wherein the housing electrode 4 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between an interior and an exterior of the housing exceeds a threshold differential pressure or a temperature at the deformable portion exceeds a threshold temperature, so as to transform the housing from a hermetically sealed housing to an open housing in fluid communication with the exterior.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

Abstract: There is provided a semiconductor device 100, comprising: at least one semiconductor chip 5, and a structure 2 thermally coupled to the at least one semiconductor chip 5, wherein the structure 2 comprises a surface located within an interior of the semiconductor device, and the surface comprises a groove 12; and a sensor 16 comprising an optical fibre 13 passing through the groove 12, wherein the sensor 16 is configured to sense a temperature of the at least one semiconductor chip 5.

Abstract: We disclose herein a semiconductor device sub-assembly comprising a plurality of semiconductor units of a first type, a plurality of semiconductor units of a second type; a plurality of conductive blocks operatively coupled with the plurality of semiconductor units, a conductive malleable layer operatively coupled with the plurality of conductive blocks, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly. At least one semiconductor unit of a second type is configured to withstand an applied pressure greater than a threshold pressure.

Abstract: We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a semiconductor unit locator comprising a plurality of holes, wherein each semiconductor unit is located in each hole of the semiconductor unit locator; a plurality of pressure means for applying pressure to each semiconductor unit, and a conductive malleable layer located between the plurality of pressure means and the semiconductor unit locator.

Abstract: We disclose herein a semiconductor device sub-assembly comprising a plurality of semiconductor units of a first type, a plurality of semiconductor units of a second type; a plurality of conductive blocks operatively coupled with the plurality of semiconductor units, a conductive malleable layer operatively coupled with the plurality of conductive blocks, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly. At least one semiconductor unit of a second type is configured to withstand an applied pressure greater than a threshold pressure.

Abstract: We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a plurality of conductive blocks, wherein each conductive block is operatively coupled with each semiconductor unit; a conductive malleable layer operatively coupled with each conductive block, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly.

Abstract: We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a plurality of conductive blocks, wherein each conductive block is operatively coupled with each semiconductor unit; a conductive malleable layer operatively coupled with each conductive block, wherein the plurality of conductive blocks are located between the conductive malleable layer and the plurality of semiconductor units. In use, at least some of the plurality of conductive blocks are configured to apply a pressure on the conductive malleable layer, when a predetermined pressure is applied to the semiconductor device sub-assembly.

Abstract: We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a semiconductor unit locator comprising a plurality of holes, wherein each semiconductor unit is located in each hole of the semiconductor unit locator; a plurality of pressure means for applying pressure to each semiconductor unit, and a conductive malleable layer located between the plurality of pressure means and the semiconductor unit locator.