Abstract: A CPU with an interface to two different RAMs which operate at different rates. The interface circuit includes a decoder which examines the addresses from the CPU and determines whether a faster cycle or slower cycle is needed. The slow RAM provides video signals to a video display. The fast RAM includes an image of the video signals stored in the first RAM. When the video signals are read by the CPU, they are read only from the fast RAM, however, when it is necessary to update the video signals, they are written into both the slow and fast RAMs.

Abstract: An enhanced video graphics controller for converting digital signals to a video signal is described. The controller is capable of displaying composite or analog RGB colors as well as providing shades of grey on monochrome displays. The processing of graphics information includes arranging 256 colors into 16 palettes of 16 colors each and is stored in a first memory. Pointers are assigned to each scan line of a frame of a display and these pointers are also stored in the first memory. Data fields which represent bit mapped video data are also stored in the first memory. For each scan line, a corresponding pointer is selected and this pointer selects one of the palettes to be loaded into a second memory. Then data field for that scan line address the second memory to provide color to the stored video data.

Abstract: An improved method and apparatus for converting a serial bit stream representative of a composite color video signal to RGB control signals is described. A sliding window is used to determine the video color for each new bit in the stream after the bits are rearranged to their proper order. As soon as a change in color is detected, the prior color is used until a predetermined condition occurs such as the passage of a predetermined number of bits. This prevents displaying of transitional colors which appear as shadows on the display.