Abstract: In a transistor structure, a 2D channel material is formed after fabrication of a gate insulator and gate (electrode). In accordance with some exemplary “channel-material last” embodiments, a contact area between the 2D channel material and a source terminal and/or drain terminal is much larger than an edge or layer thickness of the 2D channel material, which may only be a few nanometers, for example. This larger contact area may significantly reduce external resistance of a transistor structure. Doping and strain engineering may also be more successfully applied to the “channel-material last” transistor structures disclosed herein, further boosting transistor performance.

Abstract: Disclosed herein are S/D contact metallization techniques for integrated circuit (IC) structures, and related methods and devices. In one aspect, an IC structure fabricated using the S/D contact metallization method described herein may include a transistor including a region, where the region may be either a source region or a drain region of the transistor, and the IC structure may further include a contact structure in conductive contact with the region. In such an IC structure, the contact structure may include a layer including a first metal, a fill material including a second metal, and a semiconductor material at the at least a portion of an interface between the layer and the fill material.

Abstract: Integrated circuit (IC) structures with lined source or drain regions, as well as related method and devices, are disclosed. In one aspect, an IC structure may include a channel region of a transistor, a first region proximate to a first end of the channel region, and a second region proximate to a second end of the channel region, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor, the first region includes a liner material and a fill material, the liner material is laterally between the fill material and the channel region, and a material composition of the liner material is different from a material composition of the fill material.

Abstract: Disclosed herein are gate metallization techniques for integrated circuit (IC) structures, and related methods and devices. In one aspect, a resulting IC structure may include a nanoribbon comprising a semiconductor material, and a P-type transistor comprising a gate electrode at least partially wrapping around a portion of the nanoribbon. In such an IC structure, the gate electrode includes a stack of conductive materials, the stack comprising a first conductive material, a second conductive material, and a third conductive material, wherein the second conductive material is between the first conductive material and the third conductive material and includes titanium.

Abstract: Described herein are nanoribbon transistors with lined cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a liner layer next to the gate stack, and a fill material nested within the liner layer and adjacent to the source or drain. The liner layer is a non-oxide dielectric. For example, the liner may be a low-k nitride. The liner layer may be conformally deposited, and a portion of the liner layer may extend between the gate stack and the source or drain. Using a non-oxide material prevents removal of the liner during an oxide clean step prior to nanoribbon release.

Abstract: Examples of integrated circuit (IC) structures with a merged nanoribbon-based transistor along a nanocomb transistor ribbon path are described herein. In one example, an extra wide “merged” nanoribbon-based transistor can be fabricated along the same ribbon path as a nanocomb transistor to take advantage of the area occupied by the spine of the nanocomb transistor in addition to the extra height made available by a double height cell. In one such example, a merged nanoribbon-based transistor can enable higher current while also improving the ratio of active area to dead space in the IC design.

Abstract: Disclosed herein are techniques for fabricating nanoribbon transistors of integrated circuit (IC) structures using early nanoribbon release with flowable oxide fill, and related methods and devices. The fabrication method disclosed herein is based on performing a nanoribbon release prior Pto forming source/drain (S/D) regions of transistors. Using a flowable oxide fill material may be particularly advantageous in enabling the early nanoribbon release method. In one aspect, an IC structure fabricated using early nanoribbon release with flowable oxide fill may include a base, a subfin portion extending away from the base, and a transistor comprising a stack of nanoribbons above the subfun portion, wherein an upper surface of the base includes a recess proximate to the subfin portion.

Abstract: Described herein are nanoribbon transistors and processes for forming nanoribbon transistors that include a nitride liner to protect the channel material during an oxide anneal. An oxide may be used to fill trenches between stacks of nanoribbons; the oxide is annealed, and then the oxide is recessed, forming isolation regions. Source and drain regions are formed over the isolation regions. In the resulting devices, the isolation regions have a liner layer that includes nitrogen. An additional oxide liner may be around the nitride liner.

Abstract: Techniques for tuning the NP boundary between the gate electrode materials of NMOS and PMOS transistors so that the NP boundary is closer to the PMOS transistor can enable the fabrication of a PMOS transistor that is weaker than the adjacent NMOS transistor. In one example, an IC structure includes a first nanoribbon stack and a second nanoribbon stack adjacent to the first nanoribbon stack, a first gate electrode material (e.g., including an N-type work function metal) at least partially around nanoribbons of the first stack and a second gate electrode material (e.g., including a P-type work function metal) at least partially around the nanoribbons of the second stack, where a boundary between the first gate electrode material and the second gate electrode material is closer to the second nanoribbon stack than the first nanoribbon stack.

Abstract: Techniques are provided for forming an anti-fuse bit cell having semiconductor devices with different gate dielectric thicknesses that are separated by a material structure. Example such anti-fuse bit cells may include, for instance, a memory element (e.g., a first FET) and an access device (e.g., a second FET). According to some embodiments, the memory element is formed with a thinner gate dielectric compared to the access device. A material structure is formed between the memory element and access device to improve the patterning tolerance during the formation of the different gate dielectric thicknesses. Topside or backside connections may be made to the source or drain regions of the memory element and access device to create the connections of an anti-fuse bit cell.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanoribbons (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanoribbons. The transistors include a gate structure vertically between the nanoribbons. The nanoribbons are doped at their opposing ends and/or gaps are laterally between the gate structure and the source and drain structures.

Abstract: Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.). A transistor structure may have first and second channel layers between source and drain bodies, a gate stack with a gate metal and gate dielectric between the channel layers, and a dielectric spacer between the channel layers and between the gate dielectric and one of the source and drain bodies. The dielectric spacer may have a significant (or minimal) curvature such that a width of the dielectric spacer between the channel layers is much greater (or not much greater) than widths of the dielectric spacer at the channel layers or than a minimum distance separating the gate metal between the channel layers from one of the source and drain bodies. An added or altered etch may remove sacrificial dummy gate material from between the channel layers and the gate side of the dielectric spacer.

Abstract: Gate-all-around circuit structures having differentiated release layers are described. For example, an integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. A second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Dielectric spacers are adjacent to the first gate structure and the second gate structure and vertically between adjacent ones of the first set of horizontal nanowires and the second set of horizontal nanowires. Each of dielectric spacers has a notch at a location vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.

Abstract: An integrated circuit (IC) device having complementary dielectric plugs separating gate electrodes. An IC device includes a first gate-cut plug of silicon and nitrogen between and in contact with two gate structures of transistors of a first conductivity type and a second gate-cut plug between and in contact with two gate structures of transistors of a second conductivity type, complementary to the first conductivity type, and the second gate-cut plug has within a liner of silicon and nitrogen either an airgap or a dielectric of silicon and oxygen. Pairs of gate structures of transistors having both of the first and second conductivity types are separated by first and second gate-cut plugs.

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

Abstract: Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

Abstract: Gate-all-around integrated circuit structures having differentiated internal spacers are described. For example, an integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. First dielectric spacers are adjacent to the first gate structure and vertically between adjacent ones of the first set of horizontal nanowires. A second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Second dielectric spacers are adjacent to the second gate structure and vertically between adjacent ones of the second set of horizontal nanowires. The second dielectric spacers are in contact with but discontinuous from the first dielectric spacers.

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned fork-last backbones. In an example, an integrated circuit structure includes a dielectric backbone. A first vertical stack of nanowires is laterally adjacent to and in contact with a first side of the dielectric backbone. A first epitaxial source or drain structure is at an end of the first vertical stack of nanowires. A second vertical stack of nanowires is laterally adjacent to and in contact with a second side of the backbone, the second side laterally opposite the first side. A second epitaxial source or drain structure is at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to but not merged with the first epitaxial source or drain structure.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having materials that impose either a compressive or tensile stress on the adjacent semiconductor devices to improve performance. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut is confined within the gate trench. A first gate cut is arranged between adjacent NMOS devices and includes a dielectric material that imposes a tensile stress on the NMOS devices, and a second gate cut is arranged between adjacent PMOS devices and includes a dielectric material that imposes a compressive stress on the PMOS devices.

Abstract: Integrated circuit structures having zero diffusion break and wrap-around contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure having a cut extending there through to separate a first portion of the epitaxial source or drain structure from a second portion of the epitaxial source or drain structure.