Patents by Inventor Robin H. Hodge

Robin H. Hodge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5874321
    Abstract: According to the invention, a packaged integrated circuit includes a lid attached to a base to enclose a cavity, an integrated circuit chip or chips being attached to each of the lid and base within the cavity. Preferably, the chip or chips that generate the most heat during operation of the packaged integrated circuit are attached to the lid and the lid is made of a material having good thermal conductivity such as aluminum nitride. The chips attached to the base generate relatively little heat and so do not require a heat sink to be included in the base. The packaged integrated circuit is formed in a cavity-up configuration, thereby enabling connection pins or solder balls to be formed over the entire exterior surface of the base, increasing interconnection density. Additionally, attachment of chips to both the lid and the base allows an increased number of electronic functions to be included in one packaged integrated circuit.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: February 23, 1999
    Assignee: Integrated Device Technology, Inc.
    Inventors: Thomas H. Templeton, Jr., Robin H. Hodge
  • Patent number: 5766975
    Abstract: According to the invention, a packaged integrated circuit includes a lid attached to a base to enclose a cavity, an integrated circuit chip or chips being attached to each of the lid and base within the cavity. Preferably, the chip or chips that generate the most heat during operation of the packaged integrated circuit are attached to the lid and the lid is made of a material having good thermal conductivity such as aluminum nitride. The chips attached to the base generate relatively little heat and so do not require a heat sink to be included in the base. The packaged integrated circuit is formed in a cavity-up configuration, thereby enabling connection pins or solder balls to be formed over the entire exterior surface of the base, increasing interconnection density. Additionally, attachment of chips to both the lid and the base allows an increased number of electronic functions to be included in one packaged integrated circuit.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: June 16, 1998
    Assignee: Integrated Device Technology, Inc.
    Inventors: Thomas H. Templeton, Jr., Robin H. Hodge
  • Patent number: 5448165
    Abstract: A semiconductor die is temporarily enclosed in a package. The packaged die is then electrically tested and burned in. The tested die is then removed from the package. If the die performed acceptably during test and burn-in, the die is retained and either used in a production integrated circuit or sold as an unpackaged individual die. The method is simple, inexpensive, and provides semiconductor dice of high reliability (packaged die yields approach 100%). Existing test and production facilities, equipment and process flows may be used with, at most, minor changes to process a semiconductor die for any application. Semiconductor dice processed by the method are particularly useful for complex and/or costly packaging options, e.g., multichip modules, hybrid circuits or chip-on-board.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: September 5, 1995
    Assignee: Integrated Device Technology, Inc.
    Inventors: Robin H. Hodge, Thomas H. Templeton, Jr.
  • Patent number: 4420767
    Abstract: A thermally balanced leadless microelectronic circuit chip carrier in which the chip is mounted directly on a heat sinking member by means of a conductive stress relieving polyimide. The heat sinking member, which has a support surface for the chip and an extending threaded shaft, is held by a carrier member thermally compatible with the surface on which the package is to be used. The shaft passes through the carrier member and receiving surface to a heat sinking nut which holds the package to the receiving surface. Leads on the carrier member surface are used to connect the receiving surface to the wires bonded to the chip contacts.
    Type: Grant
    Filed: August 22, 1980
    Date of Patent: December 13, 1983
    Assignee: Zilog, Inc.
    Inventors: Robin H. Hodge, Mark A. Brodsky