Abstract: A fast memory system including one or more asymmetrical sense amplifiers precharged to a first logic state and optimized to slew very fast towards the first logic state. Each sense amplifier is coupled to a corresponding pair of complementary bit lines, which are preferably precharged. When enabled, each sense amplifier tends towards an opposite, default logic state opposite the first logic state when sensing the precharged bit lines. Control logic enables a corresponding precharge amplifier to precharge the bit lines, and then enables the sense amplifier after the assertion of a clock signal. Also, the control logic enables a corresponding pull-up device to precharge the output of each sense amplifier. Thus, the sense amplifier begins in the first, precharged logic state and slews towards the opposite, default logic state. The control logic then asserts a word line select signal to a corresponding memory cell, which drives a voltage differential on the bit lines to assert a data bit.

Abstract: A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized.