Patents by Inventor Robin Hsieh
Robin Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8114745Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: GrantFiled: April 14, 2010Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Publication number: 20100203691Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: ApplicationFiled: April 14, 2010Publication date: August 12, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Patent number: 7719064Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: GrantFiled: April 10, 2008Date of Patent: May 18, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Patent number: 7423319Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.Type: GrantFiled: December 28, 2006Date of Patent: September 9, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Robin Hsieh, Tsai Chun Lin, Albert Yao, Pai-Kang Hsu, Tsung-Yi Huang, Ruey-Hsin Liu
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Publication number: 20080191291Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: ApplicationFiled: April 10, 2008Publication date: August 14, 2008Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Publication number: 20080157197Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Robin Hsieh, Tsai Chun Lin, Albert Yao, Pai-Kang Hsu, Tsung-Yi Huang, Ruey-Hsin Liu
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Patent number: 7372104Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: GrantFiled: December 12, 2005Date of Patent: May 13, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu
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Publication number: 20070132033Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.Type: ApplicationFiled: December 12, 2005Publication date: June 14, 2007Inventors: Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu, Shun-Liang Hsu