Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.

Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.

Abstract: Methods and apparatus for correcting defects, such as rounded corners and line end shortening, in patterns formed via lithography are provided. Such defects are compensated for “post-rasterization” by manipulating the grayscale values of pixel maps.

Abstract: A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8.times.8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e.g., type of object orientation, etc.) into accessing data with the WE generator being driven through a ROM.

Abstract: A rasterizer for generating pixel values for a pattern generation apparatus. The pixel values drive the printing mechanism of the pattern generation apparatus. The rasterizer receives a file defining the pattern to be printed, fractures the pattern into sub frames, rasterizes each sub frame and then coordinates the provision of the shaded pixel values to the pattern generation apparatus. The rasterizer of the present invention is comprised primarily of a host processing means for fracturing and translating the file into one or more sub frames of pixels; geometry engines for rasterizing each sub frame; beam boards for providing the pixel shading values to a pattern generation system; a serial bus for coupling the host processor means to the geometry engines and beam boards and a pixel bus for coupling each of the geometry engines to each of the beam boards.

Abstract: An improved laser pattern generation apparatus. The improved pattern generation apparatus of the present invention uses a laser beam to expose a radiant sensitive film on the workpiece to print circuit patterns on a substrate. The laser beam is aligned using a beam steering means. The laser beam is split into 32 beams to create a brush. The brush scans the workpiece through use of a rotating polygonal mirror. Each beam of the brush may have one of seventeen intensity values. The beams are modulated by an Acousto-Optical Modulator. Signals provided to the Acousto-Optical Modulator define the pattern to be generated. These signals are created by a rasterizer. Increased print speed is accomplished through the use of a wider brush and a print strategy that eliminates physical stage passes.

Abstract: A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8.times.8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e.g., type of object orientation, etc.) into accessing data with the WE generator being driven through a ROM.

Abstract: A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset.

Abstract: A probe for a logic analyzer includes a replacement plug assembly comprising those portions of probe equipment which must be specifically adapted to accommodate a selected microprocessor, and a buffer probe assembly comprising those portions of probe equipment which are adapted for use with a wide variety of microprocessors. The replacement plug assembly and the buffer probe assembly are mechanically joined and electrically coupled by a square pin connector so that the replacement plug assembly may be removed from the probe and replaced with a differently configured replacement plug assembly when a different microprocessor is to be probed. Thus only a portion of the probe is changed to retarget the probe for different microprocessors.