Abstract: A method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a system design including a design under timing analysis, an external device, and an interface between the design under timing analysis and the external device; (b) generating a timing model for the external device; and (c) constructing a timing test harness for a static timing analysis tool from the timing model for the external device and the design under timing analysis.