Patents by Inventor Robin Mcree
Robin Mcree has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260090428Abstract: Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate. In an embodiment, a portion of the first substrate extends past edge surfaces of the second substrate and the third substrate. In an embodiment, a layer surrounds the portion of the first substrate, where the layer comprises a tapered cross-sectional shape, and where a first sidewall that contacts the second substrate and the third substrate has a first height that is greater than a second height of a second sidewall that faces away from the second substrate and the third substrate.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Yi LI, Praveen SREERAMAGIRI, Ibrahim El KHATIB, Robin MCREE, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN
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Publication number: 20260084181Abstract: Embodiments disclosed herein include an apparatus that includes a scraping head that has an inner cavity with open ends and an open bottom. In an embodiment, the scraping head comprises an inner wall with a port through the inner wall, and an outer wall adjacent to the inner wall. In an embodiment, a gap is provided between the inner wall and the outer wall, and a vacuum line is fluidically coupled to the gap.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Yi LI, Praveen SREERAMAGIRI, Ibrahim El KHATIB, Robin MCREE, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN
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Publication number: 20260082934Abstract: According to the various aspects, the present methods provide for the laser-assisted dicing of semiconductor workpieces that produce semiconductor devices with glass cores having semi-transparent edges.Type: ApplicationFiled: September 13, 2024Publication date: March 19, 2026Inventors: Praveen SREERAMAGIRI, Robin McREE, Jesse JONES, Gang DUAN, Yi LI, Ibrahim EL KHATIB, Srinivas PIETAMBARAM
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Publication number: 20260077433Abstract: According to the various aspects, a present tool assembly or apparatus includes a water delivery component configured to direct water to a workpiece, and a cutting component for removing material to form cut-streets for die singulation. The present tool assembly is configured to operate to remove build-up layers and other layers from a glass core of the workpiece in a wet environment and a dry environment, at cut-street locations, and perform methods for dicing the workpiece.Type: ApplicationFiled: September 13, 2024Publication date: March 19, 2026Inventors: Praveen SREERAMAGIRI, Robin McREE, Jesse JONES, Gang DUAN, Yi LI, Ibrahim EL KHATIB, Srinivas PIETAMBARAM, Kari HERNANDEZ, Soham AGARWAL, Benjamin DUONG, Pratyush MISHRA, Pratyasha MOHAPATRA
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Patent number: 12557594Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.Type: GrantFiled: March 17, 2023Date of Patent: February 17, 2026Assignee: Intel CorporationInventors: Hong Seung Yeon, Mariano Phielipp, Yi Li, Minglu Liu, Robin McRee, Yosuke Kanaoka, Gang Duan
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Publication number: 20260005186Abstract: There may be provided a system that includes a workpiece-support assembly with a platform. The system may further include an alignment-detection assembly with an optical sensor oriented towards the platform. The system may further include a handling assembly with at least one manipulator positioned along at least a first movement plane that is substantially parallel with the platform or at least a second movement plane that is substantially perpendicular to the platform. The system may further include a bonding assembly with a dispenser positioned over the platform. The system may further include a fiducial-marking assembly with a drill oriented towards the platform. The system may further include a controller electrically connected to each of the optical sensor, the at least one manipulator, the dispenser, and the drill.Type: ApplicationFiled: June 28, 2024Publication date: January 1, 2026Inventors: Yi LI, Brandon MARIN, Zhixin XIE, Praveen SREERAMAGIRI, Ibrahim EL KHATIB, Robin McREE, Jesse JONES, Srinivas PIETAMBARAM, Gang DUAN, Manohar KONCHADY
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Publication number: 20260005042Abstract: There may be provided a system. The system may include a workpiece-support assembly that includes a platform positioned alongside a singulation axis of the system. The system may further include a material-removal assembly that includes a cutter, the cutter positioned over the platform and aligned with the singulation axis. The system may further include an irradiation assembly that includes a laser source oriented towards the singulation axis. The system may further include a separation assembly that includes a separation tool. The separation tool may include a first workpiece-engagement member positioned over a first portion of the platform at a first side of the singulation axis and a second workpiece-engagement member positioned over a second portion of the platform at an opposite side of the singulation axis, or an optical source oriented towards the singulation axis.Type: ApplicationFiled: June 28, 2024Publication date: January 1, 2026Inventors: Praveen SREERAMAGIRI, Ibrahim El KHATIB, Yi LI, Robin McREE, Jesse JONES, Gang DUAN, Manohar KONCHADY, Srinivas PIETAMBARAM, Yekan WANG, Andrew JIMENEZ, Aaron GARELICK
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Publication number: 20260001805Abstract: According to the various aspects, a hybrid panel assembly includes an edge coated glass panel that is formed using a glass panel having peripheral edges and an adhesive coating layer deposited on the peripheral edges of the glass panel. The edge coated glass panel is a subcomponent for the construction of the hybrid panel assembly. A frame is provided to surround the edge coated glass panel and the adhesive coating layer bonds the frame to the glass panel to complete the construction of the hybrid panel assembly. In an aspect, the adhesive coating layer may be deposited by a coating roller and cured by a UV source.Type: ApplicationFiled: June 27, 2024Publication date: January 1, 2026Inventors: Yi LI, Praveen SREERAMAGIRI, Ibrahim El KHATIB, Robin McREE, Jesse JONES, Srinivas PIETAMBARAM, Gang DUAN
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Patent number: 12400363Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.Type: GrantFiled: September 5, 2022Date of Patent: August 26, 2025Assignee: Intel CorporationInventors: Yi Li, Hong Seung Yeon, Nicholas Haehn, Wei Li, Raquel De Souza Borges Ferreira, Minglu Liu, Robin McRee, Yosuke Kanaoka, Gang Duan, Arnab Roy
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Publication number: 20250210586Abstract: Processes and process equipment for modifying edges of semiconductor package substrates, and semiconductor package substrates having modified edges are provided. The processes and process equipment are especially useful for semiconductor package substrates that have cores that can crack or chip during processing, such as, for example, cores comprised of glass. Semiconductor package substrates having glass cores and modified edges are also provided.Type: ApplicationFiled: December 26, 2023Publication date: June 26, 2025Inventors: Praveen SREERAMAGIRI, Ibrahim EL KHATIB, Yi LI, Robin McRee, Jesse JONES, Whitney M. BRYKS, Gang DUAN, Aaron Michael GARELICK, Zheng KANG, Anqi ZHANG, Tchefor NDUKUM, Yonggang LI, Srinivas PIETAMBARAM
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20240312819Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.Type: ApplicationFiled: March 17, 2023Publication date: September 19, 2024Inventors: Hong Seung YEON, Mariano PHIELIPP, Yi LI, Minglu LIU, Robin McREE, Yosuke KANAOKA, Gang DUAN
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Publication number: 20240178151Abstract: Embodiments disclosed herein include a package architecture. In an embodiment, the package architecture comprises a first substrate with a first fiducial mark on a surface of the first substrate. In an embodiment, the package architecture further comprises a second substrate over the first substrate, where the second substrate comprises glass and a second fiducial mark on the second substrate, and where a footprint of the second fiducial mark at least partially overlaps a footprint of the first fiducial mark.Type: ApplicationFiled: November 30, 2022Publication date: May 30, 2024Inventors: Minglu LIU, Alexander AGUINAGA, Gang DUAN, Jung Kyu HAN, Yosuke KANAOKA, Yi LI, Robin MCREE, Hong Seung YEON
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Publication number: 20240111090Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Robert A. May, Tarek Ibrahim, Shriya Seshadri, Kristof Darmawikarta, Hiroki Tanaka, Changhua Liu, Bai Nie, Lilia May, Srinivas Pietambaram, Zhichao Zhang, Duye Ye, Yosuke Kanaoka, Robin McRee
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Publication number: 20240078702Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.Type: ApplicationFiled: September 5, 2022Publication date: March 7, 2024Inventors: Yi LI, Hong Seung YEON, Nicholas HAEHN, Wei LI, Raquel DE SOUZA BORGES FERREIRA, Minglu LIU, Robin McREE, Yosuke KANAOKA, Gang DUAN, Arnab ROY
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Publication number: 20230089684Abstract: A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Yosuke Kanaoka, Robin Mcree, Gang Duan, Gautam Medhi, Huang-Ta Chen
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Publication number: 20230078395Abstract: Disclosed herein are embedded heterogeneous architectures having minimized die shift and methods for manufacturing the same. The architectures may include a substrate, a bridge, and a material attached to the substrate. The substrate may include a first subset of vias and a second subset of vias. The bridge may be located in between the first subset and the second subset of vias. The material may include a first portion located proximate the first subset of vias, and a second portion located proximate the second subset of vias. The first and second portions may define a partial boundary of a cavity formed within the substrate and the bridge may be located within the cavity.Type: ApplicationFiled: September 10, 2021Publication date: March 16, 2023Inventors: Robin Mcree, Yosuke Kanaoka, Gang Duan, Jinhe Liu, Timothy A. Gosselin
