Abstract: An Ethernet data packet including a VLAN tag header and a VLAN identification field is modified. The modification is accomplished by inserting in place of the VLAN tag header a field of the same size including selected information. The VLAN identification may be retained. The inserted field may include a first field indicating the presence of the VLAN identification field and a second field of selected information, the second field being longer than the first field.

Abstract: A multiport network device includes a multiplicity of receive queues, a multiplicity of transmit queues and a forwarding engine for transferring entries from the receive queues to the transmit queues. When a transmit queue is greater than a first hysteresis point, the forwarding engine prevents transfer of entries from a receive queue to the transmit queue and transfer of entries to the transmit queue is allowed when the length of the transmit queue falls below a second hysteresis point.

Abstract: A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals.

Abstract: A clock selector circuit for selecting a single output clock signal from a multiplicity of input clock signals, each constituted by transitions between binary states, comprises a multiplicity of D-bistables each having a clock input coupled to receive the respective one of the input clock signals, a D-input coupled to receive a hold signal common to the bistables, and an output for providing a respective hold signal. A first multiplexer has inputs coupled to receive the respective input clock signals and is operative to select in response to the selection signal one of said input signals. A second multiplexer has inputs coupled to receive the respective hold signals and is operative to select in response to the selection signal the hold signal corresponding to the clock signal selected by the first multiplexer.