Patents by Inventor Robin Sarno
Robin Sarno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10592429Abstract: Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.Type: GrantFiled: June 6, 2017Date of Patent: March 17, 2020Assignee: CROSSBAR, INC.Inventors: Mehdi Asnaashari, Robin Sarno, Ruchirkumar D. Shah
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Patent number: 10169128Abstract: Resistive switching memory architectures disclosed herein are capable of achieving fast read/write times and, particularly in the case of multi-bank parallel processing, executing many read or write operations per second. Because resistive switching memory is not guaranteed to be error free, resistive memory controllers can be programmed for error management when paired with such memory architectures. To reduce error management overhead, a dedicated error pin is provided to mitigate or avoid the need for a status read in conjunction with each read or write operation issued to a memory device. A status read can be implemented in response to an error signal on the dedicated error pin, but otherwise can be avoided.Type: GrantFiled: June 5, 2017Date of Patent: January 1, 2019Assignee: CROSSBAR, INC.Inventors: Mehdi Asnaashari, Robin Sarno, Ruchirkumar D. Shah
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Patent number: 9766830Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: GrantFiled: June 2, 2016Date of Patent: September 19, 2017Assignee: Micron Technology, Inc.Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Publication number: 20160274812Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: ApplicationFiled: June 2, 2016Publication date: September 22, 2016Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Patent number: 9368163Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: GrantFiled: September 10, 2014Date of Patent: June 14, 2016Assignee: Micron Technology, Inc.Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Patent number: 9065654Abstract: The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.Type: GrantFiled: January 15, 2013Date of Patent: June 23, 2015Assignee: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Robin Sarno
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Publication number: 20150098291Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: ApplicationFiled: September 10, 2014Publication date: April 9, 2015Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Patent number: 8848478Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: GrantFiled: September 24, 2012Date of Patent: September 30, 2014Assignee: Micron Technology, Inc.Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Publication number: 20140086000Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: ApplicationFiled: September 24, 2012Publication date: March 27, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Patent number: 8355499Abstract: The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.Type: GrantFiled: December 12, 2008Date of Patent: January 15, 2013Assignee: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Robin Sarno
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Publication number: 20100153747Abstract: The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Applicant: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Robin Sarno