Abstract: A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: A display controller in a computer system controls the output of graphics display data in a computer system having a fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a Discrete Time Oscillator (DTO) based clock divider and DCT based polyphase interpolation to upscale graphics display data from a first resolution to the panel resolution. DTO clock divider circuit synchronizes scan clocks between the input resolution and the desired output resolution. Within graphics display area, MVA.TM. display at greater color depth and resolution may be accommodated by additional DTO divider and interpolation steps.

Abstract: A digital display unit receiving a display signal with image encoded at high origin frequencies (e.g., dot clock). A display signal interface samples the display signal during source display time to generate pixel data elements representative of the images encoded in the display signal. The signal is sampled at a sampling frequency equal to origin frequency. The pixel data elements are stored in a buffer at the sampling frequency and retrieved at a slower frequency. Display signals are generated for each horizontal scan line of a digital display screen during a destination display time at this slower frequency. The destination display time is designed to be longer than the source display time, which enables the display signals to be generated from all pixel data elements. The destination display time is longer than the source display time because digital display units do not require the long non-display times present in the display signals.

Abstract: A video controller for controlling at least two video displays having independent refresh rates and pixel resolutions. In a first embodiment, two separate data paths are provided within a video controller for each video display (e.g., CRT and LCD). Taking advantage of the increased bandwidth of 64 bit wide DRAMS, data for each data path may be retrieved in separate read cycles. Each datapath may operate at its own clock frequency characteristic of refresh rate and pixel resolution. The dual data path embodiment also reduces the complexity of the software model needed to drive such dual displays. IN an alternative embodiment, a single data path may be provided within a video controller to drive data for two video displays having independent refresh rates and pixel resolutions. A data "tag" (extra bit) is attached to each word or dword passing through the data path indicating the destination (e.g., CRT or LCD) of the video data. At the output of the data path, separate FIFOs (e.g.

Abstract: An apparatus for controlling a flat panel display with reduced flicker, particularly during grey scale shading. Three shading pattern lookup tables are provided, one for each sub-pixel color (Red, Blue, Green). Each shading pattern lookup table outputs a plurality of shading pattern duty cycle signals, each representing a different shade level. The phase of the three duty cycle signal patterns may be altered by adding a predetermined offset amount to one or more of the shading pattern lookup table addresses. By altering the phases of the outputs of the shading lookup tables, peak current demand within the flat panel display may be reduced and flicker or strobing of individual pixels may be reduced or eliminated.

Abstract: A process for producing a wide range of shades in images that are presented in successive frames on image fields on opto-electronic display means having at least one illumination element at each of a plurality of pixel locations. Each pixel location, for example, may have a red, a green and a blue illumination element. The display is divided into uniformly-sized display neighborhoods.