Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

Abstract: Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage.

Abstract: Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage.

Abstract: An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.

Abstract: An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal.

Abstract: A refresh scheme for a semiconductor memory macro that comprises three-transistor dynamic random access memory (3T-DRAM) cells. Similar to an internal refresh operation, an external access command is also interpreted as a read-then-write operation. A clock cycle is partitioned as a plurality of time slots by an internal clock generator. Each time slot is assigned to execute a specific memory cell operations, whereby array idle time typically needed for performing exclusively non-array operations is no longer required. An external access and an internal refresh can be operated sequentially without degrading speed performance. An internal refresh can occur in every clock cycle period to retain the stored data. This clock cycle period is less than the time required for consecutively performing the external access and thereafter the internal refresh upon the completion of the external access.

Abstract: A system 100 which provides asynchronous SRAM functionality with a DRAM device. The system 100 includes an address transition detector circuit 102, a memory clock generator circuit 104, a refresh timer 106, a refresh address counter 108, a memory access controller 110, a memory control sequencer 112, an address buffer 114, a write data buffer 116, a three-input address multiplexer 118, a two-input data multiplexer 120, inverters 122, 124, 126, and 128, AND gates 130, 132, and 134, NOR gates 136, 138, 140, and 142, OR gate 156, and a DRAM array 144 of memory cells. The components of system 100 cooperate to selectively interrupt external memory commands, such as read and write commands, in order to perform refresh operations on array 144.

Abstract: A system 100 which provides asynchronous SRAM functionality with a DRAM device. The system 100 includes an address transition detector circuit 102, a memory clock generator circuit 104, a refresh timer 106, a refresh address counter 108, a memory access controller 110, a memory control sequencer 112, an address buffer 114, a write data buffer 116, a three-input address multiplexer 118, a two-input data multiplexer 120, inverters 122, 124, 126, and 128, AND gates 130, 132, and 134, NOR gates 136, 138, 140, and 142, OR gate 156, and a DRAM array 144 of memory cells. The components of system 100 cooperate to selectively interrupt external memory commands, such as read and write commands, in order to perform refresh operations on array 144.