Patents by Inventor Robin Van Den Nieuwenhuizen
Robin Van Den Nieuwenhuizen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8822994Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: GrantFiled: September 13, 2012Date of Patent: September 2, 2014Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Publication number: 20130072011Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: ApplicationFiled: September 14, 2012Publication date: March 21, 2013Applicants: IBM SEMICONDUCTOR RESEARCH AND DEVELOPMENT CENTER (SRDC), STMICROELECTRONICS, INC.Inventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Publication number: 20130063173Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: ApplicationFiled: September 13, 2012Publication date: March 14, 2013Applicants: IBM Semiconductor Research and Development Center (SRDC), STMicroelectronics, Inc.Inventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Patent number: 8324622Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: GrantFiled: December 31, 2009Date of Patent: December 4, 2012Assignees: STMicroelectronics Inc., International Business Machines CorporationInventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Publication number: 20110156032Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicants: STMICROELECTRONICS, INC., IBM Semiconductor Research and Development Center (SRDC)Inventors: John H. Zhang, Laertis Economikos, Robin Van Den Nieuwenhuizen, Wei-Tsu Tseng
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Patent number: 7790541Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.Type: GrantFiled: December 4, 2007Date of Patent: September 7, 2010Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (AMD)Inventors: Bruce B. Doris, Mahender Kumar, Werner A. Rausch, Robin Van Den Nieuwenhuizen
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Publication number: 20090140347Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC. (AMD)Inventors: Bruce B. Doris, Mahender Kumar, Werner A. Rausch, Robin Van Den Nieuwenhuizen