Abstract: A method for fabricating an optoelectronic device includes forming an isolation structure between an array of pixel electrodes and a built-in pad (BIP) on a dielectric layer of an integrated circuit, depositing a photosensitive film over the dielectric layer, such that at least one pinch point is formed in the photosensitive film at an edge of the isolation structure. The method further includes depositing an electrode layer, which is at least partially transparent, over the photosensitive film, etching away the photosensitive film from the BIP, and after etching away the photosensitive film, depositing a metal layer over the BIP and in contact with the electrode layer.

Abstract: The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively deposited on the sandwich layer inside the cavity. A second sacrificial layer is deposited on the first sacrificial layer and on the first Cu layer. A cavity is formed in the second sacrificial layer, exposing at least a portion of the first Cu layer. A second Cu layer is selectively deposited in the second sacrificial layer cavity including the exposed portion of the first Cu layer. The combination of the first and second Cu layers forms a Cu component. Subsequently, the first and second sacrificial layers are removed resulting in a Cu component that is free standing on the sandwich layer, such that the top and sides of the component are exposed.

Abstract: A method and apparatus for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.

Abstract: A method and apparatus for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.

Abstract: A method is provided that includes (1) receiving information about a substrate processed within a barrier/seed layer deposition subsystem from an integrated inspection system of the subsystem; (2) determining an electroplating process to perform within an electroplating subsystem based at least in part on the information received from the inspection system of the barrier/seed layer deposition subsystem; (3) directing the electroplating subsystem to deposit a fill layer on the substrate based on the electroplating process; (4) receiving information about the fill layer from an integrated inspection system of the electroplating subsystem; (5) determining a planarization process to perform within a planarization subsystem based at least in part on the information received from the inspection system of the electroplating subsystem; and (6) directing the planarization subsystem to planarize the substrate based on the planarization process.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias etches a via opening in a first insulating layer. A photoresist layer that the defines the conductive wiring is deposited and patterned on the first insulating layer after the via opening has been created. The via opening and the conductive wire opening in the resist layer are then filled with the conductive material, such as copper. The resist layer may then be removed and a second insulating layer provided over the first insulating layer.

Abstract: A method of forming a semiconductor device having selectively fabricated copper interconnect structure that is encapsulated within selectively formed metallic barriers. An exemplary encapsulated copper interconnect structure includes a first low dielectric constant layer (low K1) formed over a substantially completed semiconductor device on which a first sidewall metallic barrier, consisting of metallic material is formed to line the wall structure of a via. The metallic liner encapsulates a first, substantially thin (≦0.25 &mgr;m) copper interconnect structure. A second selectively formed thicker (>>0.25 &mgr;m) copper interconnect trench structure is formed overlying and integral with the first copper interconnect structure. A second metallic barrier is deposited over the second selectively formed copper interconnect structure and is formed integral with the first sidewall metallic barrier.

Abstract: The selectivity of an etchant to a capping layer in a Cu or Cu alloy interconnect member is significantly enhanced by providing a dielectric layer thereon with a faster etch rate. Embodiments include forming the dielectric layer with a faster etch rate by PECVD: (a) at a low frequency bias of about 0.1 kW or greater; (b) at a temperature of about 250° C. or greater; or (c) at a pressure greater than about 2.6 Torr.

Abstract: A rapid thermal anneal (>600° C.) in a nitrogen-containing atmosphere is used to form a barrier TiN layer at the bottom of contact openings. To form source and drain contacts, contact openings are etched in a dielectric down to a titanium silicide layer on top of doped regions in the semiconductor (i.e. polysilicon or doped regions in the semiconductor substrate). The barrier TiN layer on the bottom of the contact openings is provided by a rapid thermal anneal in a nitrogen-containing atmosphere which converts the top part of the titanium silicide layer in the contact openings into a barrier TiN layer. This nitrogen-containing atmosphere contains nitrogen-containing species (e.g., N2, NH3, N2O) that react with titanium silicide to form TiN under the conditions provided by the rapid thermal anneal.

Abstract: The present invention relates to the formation of a semiconductor device having selectively fabricated copper interconnect structure that is encapsulated within selectively formed metallic barriers. An exemplary encapsulated copper interconnect structure includes a first low dielectric constant layer (low K1) formed over a substantially completed semiconductor device on which a first sidewall metallic barrier, consisting of metallic material, such as tantalum (Ta), tantalum nitride (TaN) and tungsten nitride WN, is formed to line the wall structure of a via. The metallic liner encapsulates a first, substantially thin (≦0.25 &mgr;m) copper interconnect structure. A second selectively formed thicker (>>0.25 &mgr;m) copper interconnect trench structure is formed overlying and integral with the first copper interconnect structure.

Abstract: Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by depositing the capping layer under high density plasma conditions at an elevated temperature, such as about 450° C. to about 650° C., e.g. about 450° C. to about 550° C. High density plasma deposition at such elevated temperatures increases the surface roughness of the exposed Cu metallization, thereby increasing adhesion of the deposited capping layer, such as silicon nitride and increasing the density of the silicon nitride capping layer thereby improving its etch stop characteristics. Embodiments of the present invention include treating the exposed surface of the Cu or Cu alloy interconnect member after CMP in a hydrogen-containing plasma, and depositing a silicon nitride capping layer under high density plasma conditions on the treated surface.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, with an ammonia-containing plasma and then depositing the capping layer, e.g., silicon nitride, under high density plasma conditions at an elevated temperature, such as about 450.degree. C. to about 650.degree. C., e.g. about 450.degree. C. to about 550.degree. C. High density plasma deposition at such elevated temperatures increases the surface roughness of the exposed Cu metallization, thereby further increasing adhesion of the silicon nitride capping layer and increasing the density of the silicon nitride capping layer, thereby improving its etch stop characteristics.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias etches a via opening in a first insulating layer. A photoresist layer that the defines the conductive wiring is deposited and patterned on the first insulating layer after the via opening has been created. The via opening and the conductive wire opening in the resist layer are then filled with the conductive material, such as copper. The resist layer may then be removed and a second insulating layer provided over the first insulating layer.

Abstract: An aluminum fill process for sub-0.25 .mu.m technology integrated circuits that has a reflow temperature less than 400.degree. C. that has low alloy resistivity and excellent electromigration characteristics. The aluminum allow is composed of Al-1% Ge-1% Cu.

Abstract: A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.

Abstract: In-laid metal, e.g., copper or copper alloy, contacts and conductive routing patterns are formed in recesses in the surface of a substrate by a damascene-type process, comprising depositing a layer of an electrically conductive material filling the recesses and covering the substrate surface, reducing the thickness of the layer by a process providing a faster rate of layer removal than that obtained by chemical-mechanical polishing (CMP), and subjecting the remaining layer thickness to CMP processing to (a) substantially remove the remaining layer thickness and (b) render the exposed upper surface of the material filling the recesses substantially coplanar with the substrate surface, whereby increased manufacturing throughput, greater planarity, and reduced defects are obtained.

Abstract: High aspect ratio openings in excess of 3, such as trenches, via holes or contact holes, in a dielectric layer are voidlessly filled employing a pulse or forward-reverse pulse electroplating technique to deposit copper or a copper-base alloy. A leveling agent is incorporated in the electroplating composition to ensure that the opening is filled substantially sequentially from the bottom upwardly.

Abstract: An improved process for manufacturing cobalt silicide layers uses two capping layers. A first capping layer of titanium nitride prevents the formation of a cobalt/titanium intermetallic. A subsequently formed titanium metallic layer getters impurities from outgassing and the ambient preventing corruption of the cobalt layer. Two rapid thermal annealing steps convert the cobalt at the cobalt/silicon intermetallic into highly conductive cobalt disilicide. The cobalt silicide does not suffer from linewidth dependent increases in resistivity. Therefore, the cobalt disilicide formed by the present method is useful for semiconductor devices with linewidths and feature sizes less than 0.20 .mu.m. The process has wide applicability and may be used to fabricate local circuit interconnects, floating gates, double polysilicon stacked floating gates as well as other uses.

Abstract: The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.