Patents by Inventor Robinson Quiazon

Robinson Quiazon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor flip chip package having substantially non-collapsible spacer and method of manufacture thereof
    Patent number: 8405230
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 26, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Marie L. Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Rodriguez Dahilig
  • SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110108970
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Marie L. Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
  • Semiconductor flip chip package having substantially non-collapsible spacer
    Patent number: 7880313
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: February 1, 2011
    Assignee: Chippac, Inc.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
  • Integrated circuit encapsulation system with vent
    Patent number: 7482683
    Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: January 27, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Erick Dahilig, Sheila Marie L. Alvarez, Robinson Quiazon, Jose Alvin Caparas
  • Integrated circuit package system with downset lead
    Patent number: 7443015
    Abstract: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: October 28, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Sheila Marie L. Alvarez, Jose Alvin Caparas, Robinson Quiazon
  • Etched leadframe flipchip package system
    Patent number: 7414318
    Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: August 19, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Hin Hwa Goh, Robinson Quiazon
  • INTEGRATED CIRCUIT ENCAPSULATION SYSTEM WITH VENT
    Publication number: 20070262423
    Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Antonio Dimaano, Erick Dahilig, Sheila Marie Alvarez, Robinson Quiazon, Jose Caparas
  • ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
    Publication number: 20070241432
    Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.
    Type: Application
    Filed: June 20, 2007
    Publication date: October 18, 2007
    Inventors: Il Kwon Shim, Sheila Alvarez, Hin Hwa Goh, Robinson Quiazon
  • Etched leadframe flipchip package system
    Patent number: 7250685
    Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.
    Type: Grant
    Filed: February 4, 2006
    Date of Patent: July 31, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Hin Hwa Goh, Robinson Quiazon
  • ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
    Publication number: 20070108565
    Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.
    Type: Application
    Filed: February 4, 2006
    Publication date: May 17, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Sheila Marie Alvarez, Hin Hwa Goh, Robinson Quiazon
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWNSET LEAD
    Publication number: 20070108624
    Abstract: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.
    Type: Application
    Filed: May 4, 2006
    Publication date: May 17, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Jeffrey Punzalan, Sheila Alvarez, Jose Caparas, Robinson Quiazon
  • Semiconductor package flip chip interconnect having spacer
    Publication number: 20060192295
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Application
    Filed: November 17, 2005
    Publication date: August 31, 2006
    Applicant: ChipPAC, Inc.
    Inventors: Jae Lee, Geun Kim, Sheila Alvarez, Robinson Quiazon, Hin Goh, Frederick Dahilig