Abstract: A digital transmitter (13) for transmitting serial words of predetermined length at selected speeds for output at a plurality of parallel channels (120, 120'). The words selected for series transmission at said parallel output channels (120, 120') are sequentially repeatedly applied to a multiplexer (89) which forwards selected bits from these words at fixed and variably setable speeds to a selected shift register (101 or 102) and latch (105 or 106), combination for output transmission.

Abstract: A power loss analyzer for providing a signal processor with a discrete power loss alert signal indicative of an imminent power disruption and for providing to the processor subsequent to a disruption a discrete power loss signal indicative of a power disruption that has resulted in degradation of the data stored in memory is disclosed.

Abstract: A digital circuit discriminates between valid transitions in the level of a two level logic signal in which the signal remains at its new level for a predetermined time period, and those transitions in the level of the logic signal which may be caused by noise. Upon the transition of the logic signal from one level to another, a timer is actuated. If the logic signal remains in its new level until the timer expires, the transition is considered valid and an output signal indicative thereof is produced. If the logic signal reverts to its initial level before the timer expires, the transition is considered invalid, the timer is reset and no output signal is produced. A discrete output is produced when a valid transition occurs between either of the two separate logic signal levels.