Patents by Inventor Rocendo Bracamontes
Rocendo Bracamontes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160378209Abstract: Particular embodiments described herein provide for a stylus that includes a body, a plurality of conductive traces, a resonance circuit, and a tip, wherein the tip can be used to interact with both an electromagnetic resonance touchscreen and a capacitive touchscreen. The conductive traces can be spaced such that the conductive traces do not substantially block a resonance frequency of the resonance circuit.Type: ApplicationFiled: June 27, 2015Publication date: December 29, 2016Applicant: Intel CorporationInventors: Hong W. Wong, Zhiming Jim Zhuang, Shwetank Kumar, Rocendo Bracamontes, Arvind Kumar, Murali Veeramoney
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Elastic shared RAM array including contiguous instruction and data portions distinct from each other
Patent number: 8533439Abstract: A microcontroller, system and method are provided. In one implementation, a microcontroller is provided that includes a first memory operable to store instructions for normal operational use of the microcontroller, a second memory operable to store patch code instructions during debugging of the instructions within the first memory, and a central processing unit (CPU) operable to fetch instructions from the first memory and the patch code instructions from the second memory. The second memory is further operable to store the instructions for normal operational use of the microcontroller or data after the debugging of the instructions within the first memory is completed.Type: GrantFiled: November 7, 2005Date of Patent: September 10, 2013Assignee: Atmel CorporationInventor: Rocendo Bracamontes -
Patent number: 8316174Abstract: Some embodiments includes a digital control system having a microcontroller to handle a first command associated with a first operation of a memory device, and circuitry coupled to the microcontroller to handle a second command associated with a second operation of the memory device without involving the microcontroller in the second operation.Type: GrantFiled: September 29, 2009Date of Patent: November 20, 2012Assignee: Atmel CorporationInventors: Daniel S. Cohen, Matthew Todd Wich, Jason J. Ziomek, Rocendo Bracamontes, Shude Lu
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Patent number: 7814250Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.Type: GrantFiled: April 27, 2007Date of Patent: October 12, 2010Assignee: Atmel CorporationInventor: Rocendo Bracamontes Del Toro
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Patent number: 7769933Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.Type: GrantFiled: April 27, 2007Date of Patent: August 3, 2010Assignee: Atmel CorporationInventor: Rocendo Bracamontes Del Toro
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Patent number: 7761632Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.Type: GrantFiled: April 27, 2007Date of Patent: July 20, 2010Assignee: Atmel CorporationInventor: Rocendo Bracamontes Del Toro
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Patent number: 7743186Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.Type: GrantFiled: April 27, 2007Date of Patent: June 22, 2010Assignee: Atmel CorporationInventor: Rocendo Bracamontes Del Toro
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Publication number: 20100017563Abstract: Some embodiments includes a digital control system having a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control, and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug. Other embodiments are described.Type: ApplicationFiled: September 29, 2009Publication date: January 21, 2010Applicant: Atmel CorporationInventors: Daniel Scott Cohen, Mathew Todd Wich, Jason Joseph Ziomek, Rocendo Bracamontes, Shude Lu
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Patent number: 7600090Abstract: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.Type: GrantFiled: November 28, 2005Date of Patent: October 6, 2009Assignee: Atmel CorporationInventors: Daniel Scott Cohen, Mathew Todd Wich, Jason Joseph Ziomek, Rocendo Bracamontes, Shude Lu
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Patent number: 7551016Abstract: An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the frequency divider multiplied by two.Type: GrantFiled: February 4, 2005Date of Patent: June 23, 2009Assignee: Atmel CorporationInventor: Rocendo Bracamontes del Toro
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Publication number: 20080270667Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Atmel CorporationInventor: Rocendo Bracamontes Del Toro
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Publication number: 20080270655Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Atmel CorporationInventor: Rocendo Bracamontes Del Toro
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Publication number: 20080270650Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Atmel CorporationInventor: Rocendo BRACAMONTES DEL TORO
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Publication number: 20080270656Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Atmel CorporationInventor: Rocendo BRACAMONTES DEL TORO
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Publication number: 20080040580Abstract: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.Type: ApplicationFiled: November 28, 2005Publication date: February 14, 2008Inventors: Daniel Scott Cohen, Mathew Todd Wich, Jason Joseph Ziomek, Rocendo Bracamontes, Shude Lu
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Publication number: 20070106884Abstract: A microcontroller, system and method are provided. In one implementation, a microcontroller is provided that includes a first memory operable to store instructions for normal operational use of the microcontroller, a second memory operable to store patch code instructions during debugging of the instructions within the first memory, and a central processing unit (CPU) operable to fetch instructions from the first memory and the patch code instructions from the second memory. The second memory is further operable to store the instructions for normal operational use of the microcontroller or data after the debugging of the instructions within the first memory is completed.Type: ApplicationFiled: November 7, 2005Publication date: May 10, 2007Inventor: Rocendo Bracamontes
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Publication number: 20060176097Abstract: An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the frequency divider multiplied by two.Type: ApplicationFiled: February 4, 2005Publication date: August 10, 2006Inventor: Rocendo Bracamontes del Toro