Patents by Inventor Rocendo Bracamontes del Toro

Rocendo Bracamontes del Toro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7814250
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: October 12, 2010
    Assignee: Atmel Corporation
    Inventor: Rocendo Bracamontes Del Toro
  • Patent number: 7769933
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: August 3, 2010
    Assignee: Atmel Corporation
    Inventor: Rocendo Bracamontes Del Toro
  • Patent number: 7761632
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: July 20, 2010
    Assignee: Atmel Corporation
    Inventor: Rocendo Bracamontes Del Toro
  • Patent number: 7743186
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: June 22, 2010
    Assignee: Atmel Corporation
    Inventor: Rocendo Bracamontes Del Toro
  • Patent number: 7551016
    Abstract: An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the frequency divider multiplied by two.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: June 23, 2009
    Assignee: Atmel Corporation
    Inventor: Rocendo Bracamontes del Toro
  • Publication number: 20080270650
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: Atmel Corporation
    Inventor: Rocendo BRACAMONTES DEL TORO
  • Publication number: 20080270655
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: Atmel Corporation
    Inventor: Rocendo Bracamontes Del Toro
  • Publication number: 20080270656
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: Atmel Corporation
    Inventor: Rocendo BRACAMONTES DEL TORO
  • Publication number: 20080270667
    Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: Atmel Corporation
    Inventor: Rocendo Bracamontes Del Toro
  • Publication number: 20060176097
    Abstract: An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the frequency divider multiplied by two.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 10, 2006
    Inventor: Rocendo Bracamontes del Toro