Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.

Abstract: An electric control device generates control signals that control electrical devices. The control device has a multiplicity of control modules. At least some of the control modules have a comparator for comparing two values and they function in dependence on the various outcomes of comparison. One of more global comparators are provided for certain comparisons in the control device. Each of the global comparators operates on several or all of the control modules. The control modules operate not only in dependence on the comparisons in their respective comparators, but additionally in dependence on the comparison results in the global comparator.

Abstract: A microprocessor includes a processor unit with an internal bus and a programmable bus control unit with an external bus. The bus control unit interconnects the internal bus with the external bus through multiplexers, latches and control logic. An 8 and 16-bit multiplexed bus mode and an 8 and 16-bit non-multiplexed bus mode are programmable. The bus control unit generates all of the necessary control signals adjusting their timing to the respective bus type. Different bus configurations can be selected for several address ranges through different control registers. The timing of the bus signals is programmable to allow slower peripherals to be connected to the microprocessor.

Abstract: A microprocessor assembly includes an integrated microprocessor and an external bus having a plurality of signal lines and a corresponding number of terminals connected to the integrated microprocessor. The integrated microprocessor includes a plurality of terminals; a core processor; at least one quasi-external bus having a plurality of signal lines; a bus control unit connecting the core processor to the quasi-external bus; a device connecting the quasi-external bus to the external bus through a corresponding number of terminals; and at least one peripheral connected to the quasi-external bus. The quasi-external bus has at least the same number of signal lines carrying the same signal as the external bus, and the quasi-external bus has the same control performance as the external bus, for connecting a peripheral without modification to both the external bus and the quasi-external bus.

Abstract: An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, includes a memory; an address register having contents pointing to an instruction to be processed in said memory; an instruction register for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit for calculating addresses; an incrementing stage for incrementing the contents of said address register; and a multiplexer for selecting a calculated address or an incremented successor address. One embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit. Another embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit.

Abstract: A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources. A common interrupt bus is connected to the peripheral interrupt nodes and to the central interrupt node. The method for priority selection includes activating the interrupt bus in a prioritizing round in accordance with a priority value with a peripheral interrupt node assigned to an interrupt source in the presence of an interrupt request of the interrupt source.

Abstract: A circuit configuration for improving the resolution of successive pulsed signals over time includes first and second counters each having one clock input, the clock input of the first counter being supplied with a first clock signal, and the clock input of the second counter being supplied with a second clock signal having a n-multiple frequency of the first clock signal. The first counter has a control input and a counter output, the control input of the first counter being supplied with successive pulsed signals. The second counter has a counter input, an overflow output and a write input, the write input of the second counter being connected to the overflow output of the second counter.

Abstract: A counter/timer circuit for a microcontroller includes a central register and two auxiliary registers each having transfer outputs and counting inputs. Bistable output storage elements are each connected to a respective one of the transfer outputs. Interrupt request flags are also each connected to a respective one of the transfer outputs. Start/stop elements are each connected to a respective one of the counting inputs. Input control blocks are each connected to a respective one of the start/stop elements. First reload, capture and compare units are connected between one of the auxiliary registers and the central register, and second reload, capture and compare units are connected between the other of the auxiliary registers and the central register.