Abstract: A transceiver module for coupling between cells in a distributed intelligence network and a twisted pair line. The module receives power from the line and provides power to its respective cell. At the end of transmitting a packet, the transceiver transmits a code violation, then an anti-code violation to dissipate energy in the line. This is followed by clamping the line for the dead time between packets. N transceivers may be connected (without a cell) to form a repeater. The transceiver module may be used in a network having free topology; that is, an ideal transmission line, with terminators is not needed.

Abstract: An apparatus useful in the configuration of communication network. The present invention provides for improved apparatus and techniques for configuration of network nodes. In particular, what is described is a device which may be coupled with each node of a network. When coupled to a node, the device and node cooperate in allowing communication of information identifying the node and the node type to the device. The node identification and type information may then be utilized to reliably complete configuration of a network.

Abstract: A transceiver module for coupling between cells in a distributed intelligence network and a twisted pair line. The module receives power from the line and provides power to its respective cell. At the end of transmitting a packet, the transceiver transmits a code violation (pulse), then an anti-code violation (pulse of opposite polarity) to dissipate energy in the line. This is followed by clamping the line for the dead time between packets. N transceivers may be connected (without a cell) to form a repeater. The transceiver module may be used in a network having free topology; that is, an ideal transmission line, with terminators is not needed.

Abstract: A specialized apparatus and method for providing fast programmed I/O for transferring information in a multi-processor environment which includes a CPU, and a memory coupled to an I/O port across an internal data bus. Multiple bytes of data are transferred in successive processing cycles to the I/O port from the memory, or from the I/O to the memory by first determining the upper limit for the number of bytes that are going to be transferred. This number and the memory start address are then stored in CPU registers. The I/O module is then checked by the CPU to see if a data byte is available from an external device. If a data byte is available, the I/O module is instructed to place the data byte on the bus for storage within the memory at the start address. The address is then incremented and the count is decremented. The above procedure is repeated until the count drops to zero, after which time the next instruction is fetched.

Abstract: An interface between a network cell and an associated network communications transceiver passes both network information and command/control information between the cell and the transceiver. The interface is designed to minimize the number of control lines between the cell and the transceiver. A protocol between the two devices is established to deal with configuration and error reporting as well as the passage of network data. This protocol consists of the cell and the transceiver each exchanging 8 bits of status and 8 bits of data simultaneously and continuously at rates up to 1.25 MBPS. Only a single version of cell firmware is required since a fixed amount of configuration information is sent from the cell to the transceiver, and a fixed amount of status information is returned from the transceiver to the cell.

Abstract: An improved architecture for a computerized branch exchange particularly for a time division multiplexed bus used in the exchange. An intershelf bus includes a unidirectional source bus which receives signals from expanders and a unidirectional destination bus which transmits signals to the expanders. The expanders, through another bus, communicate with line cards which interface with telephone station sets, commercial lines, etc. A time division multiplexed controller updates distributed connection tables contained in each of the expanders and controls the flow of data onto and from the unidirectional buses. The distributed connection tables eliminate the need to broadcast addresses during each time slot. The arrangement is particularly useful in reducing blocking associated with prior art bidirectional buses.