Abstract: A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.

Abstract: A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. The stacked PCM RF switches can include a high shunt capacitance PCM RF switch having its heating element contacts near its PCM contacts, and a low shunt capacitance PCM RF switch having its heating element contacts far from its PCM contacts. An RF voltage is substantially uniformly distributed between the high shunt capacitance PCM RF switch and the low shunt capacitance PCM RF switch. The stacked PCM RF switches can also include a wide heating element PCM RF switch having a large PCM active segment, and a narrow heating element PCM RF switch having a small PCM active segment. The wide heating element PCM RF switch will have a higher breakdown voltage than the narrow heating element PCM RF switch.

Abstract: A radio frequency (RF) transistor includes a drain, a source, and a gate. A first dielectric having a first dielectric constant is over the source and the drain. A gap is in the first dielectric and over the gate, the gap extending to the gate. A second dielectric is situated in the gap. The second dielectric has a second dielectric constant substantially less than the first dielectric constant so as to reduce a COFF of the RF transistor. The RF transistor can be part of a stack of RF transistors in an RF switch. The RF switch can be situated between an antenna and an amplifier.

Abstract: A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions.

Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.

Abstract: A bi-directional ESD protection device for an RF circuit that utilizes two pre-driver FETs to reliably maintain the gate voltage of a ggNMOS-type main transistor the lowest applied voltage (e.g., 0V) in order to maximize the main transistor's drain-to-source breakdown voltage, which determines the trigger voltage of the ESD protection device. One pre-driver FET couples the main transistor's gate to ground during positive voltage input signal phases, and the other pre-driver FET couples the main transistor's gate to the input signal path during negative voltage input signal phases. While the amplitude of the input signals remains below the main transistor's trigger voltage, the main transistor remains completely turned off, whereby the input signals are passed to I/O circuitry with minimal interference. Whenever the input signal exceeds the trigger voltage, the main transistor turns on to shunt the over-voltage/current to ground, thereby protecting the I/O circuitry.

Abstract: A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.

Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. The stacked PCM RF switches can include a high shunt capacitance PCM RF switch having its heating element contacts near its PCM contacts, and a low shunt capacitance PCM RF switch having its heating element contacts far from its PCM contacts. An RF voltage is substantially uniformly distributed between the high shunt capacitance PCM RF switch and the low shunt capacitance PCM RF switch. The stacked PCM RF switches can also include a wide heating element PCM RF switch having a large PCM active segment, and a narrow heating element PCM RF switch having a small PCM active segment. The wide heating element PCM RF switch will have a higher breakdown voltage than the narrow heating element PCM RF switch.

Abstract: A high power semiconductor switch including a plurality of transistor switch circuits connected in series between first and second ports. A first set of transistor switch circuits is located immediately adjacent to the first port, a second set of transistor switch circuits is located immediately adjacent to the second port, and a third set of transistor switch structures are located between the first and second sets. Each transistor switch circuit of the first and second set includes a switching transistor and a dynamic impedance circuit, wherein the dynamic impedance circuit reduces the effective impedance of the corresponding switching transistor when an RF signal is being transmitted. The dynamic impedance circuits are designed to reduce and equalize the voltage drops across the switching transistors of the first and second sets.

Abstract: A non-linear shunt circuit is coupled in a shunt-type configuration (e.g., parallel to an RF switch shunt branch) between a main signal line and ground in an RF circuit, and includes a harmonic cancellation element (HCE) (e.g., back-to-back diodes or diode-connected FETs) configured to cancel third harmonics generated on the main signal line by operation of an RF switch. The RF switch includes a series branch made up of multiple FETs coupled in series in the main signal line between a transmitter/receiver circuit and an antenna. The HCE is coupled to the main signal line either by way of a mid-point node or an input/output terminal of the RF switch's series branch. The non-linear shunt circuit also includes optional protection circuits that provide frequency-independent impedance through the HCE. Various techniques (e.g., active biasing) are optionally utilized to increase effectiveness to a wider range of the switch input power levels.

Abstract: A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.

Abstract: A semiconductor structure includes a plurality of source/drain regions, a plurality of channel/body regions located between the source/drain regions, and a polysilicon gate structure located over the plurality of channel/body regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, each extending over a corresponding one of the channel/body regions. Each polysilicon gate finger includes first and second rectangular portions that extend in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along the first axis. This offset results in each source/drain region having a first section with a first length, and a second section with a second length, greater than the first length. A single column of contacts are provided in the first section of each source/drain region, and multiple columns of contacts are provided in the second section of each source/drain region.

Abstract: A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions.

Abstract: A non-linear shunt circuit is coupled in a shunt-type configuration (e.g., parallel to an RF switch shunt branch) between a main signal line and ground in an RF circuit, and includes a harmonic cancellation element (HCE) (e.g., back-to-back diodes or diode-connected FETs) configured to cancel third harmonics generated on the main signal line by operation of an RF switch. The RF switch includes a series branch made up of multiple FETs coupled in series in the main signal line between a transmitter/receiver circuit and an antenna. The HCE is coupled to the main signal line either by way of a mid-point node or an input/output terminal of the RF switch's series branch. The non-linear shunt circuit also includes optional protection circuits that provide frequency-independent impedance through the HCE. Various techniques (e.g., active biasing) are optionally utilized to increase effectiveness to a wider range of the switch input power levels.