Patents by Inventor Roderick A. B. Devine

Roderick A. B. Devine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7459403
    Abstract: In microelectronic circuits involving dielectric/semiconductor interfaces having interstitial sites in the dielectric, a method for hardening these interfaces by introducing a small atomic diameter inert gas into the interstitial sites.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: December 2, 2008
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Roderick A. B. Devine, Harold L. Hughes, Akos G. Revesz
  • Publication number: 20030022527
    Abstract: A method of radiation hardening microcircuits including the steps of removing hydrogen from the microcircuit in a vacuum furnace and annealing in deuterium-containing forming gas.
    Type: Application
    Filed: June 21, 2001
    Publication date: January 30, 2003
    Inventors: Roderick A. B. Devine, Joseph R. Chavez
  • Patent number: 6304666
    Abstract: An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials created by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: October 16, 2001
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: William L. Warren, Roderick A. B. Devine
  • Patent number: 6159829
    Abstract: An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: December 12, 2000
    Inventors: William L. Warren, Karel J. R. Vanheusden, Daniel M. Fleetwood, Roderick A. B. Devine, Leo B. Archer, George A. Brown, Robert M. Wallace
  • Patent number: 6140157
    Abstract: An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: October 31, 2000
    Assignees: Sandia Corporation, Science & Technology Corporation at University of New Mexico, France Telecom/CNET
    Inventors: William L. Warren, Karel J. R. Vanheusden, Daniel M. Fleetwood, Roderick A. B. Devine
  • Patent number: 5830575
    Abstract: An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: November 3, 1998
    Assignee: Sandia National Laboratories
    Inventors: William L. Warren, Karel J. R. Vanheusden, Daniel M. Fleetwood, Roderick A. B. Devine
  • Patent number: 5786231
    Abstract: A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: July 28, 1998
    Assignee: Sandia Corporation
    Inventors: William L. Warren, Karel J. R. Vanheusden, James R. Schwank, Daniel M. Fleetwood, Marty R. Shaneyfelt, Peter S. Winokur, Roderick A. B. Devine