Patents by Inventor Roderick C. Frianeza

Roderick C. Frianeza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory page boosting method, device and system
    Patent number: 8050090
    Abstract: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: November 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Seiichi Aritome, Jeffrey C. Antosh, Roderick C. Frianeza
  • MEMORY PAGE BOOSTING METHOD, DEVICE AND SYSTEM
    Publication number: 20100232222
    Abstract: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells.
    Type: Application
    Filed: May 26, 2010
    Publication date: September 16, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Seiichi Aritome, Jeffrey C. Antosh, Roderick C. Frianeza
  • Memory page boosting method, device and system
    Patent number: 7738291
    Abstract: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: June 15, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Seiichi Aritome, Jeffrey C. Antosh, Roderick C. Frianeza
  • Memory page boosting method, device and system
    Publication number: 20080225589
    Abstract: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells.
    Type: Application
    Filed: March 12, 2007
    Publication date: September 18, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Seiichi Aritome, Jeffrey C. Antosh, Roderick C. Frianeza