Abstract: A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.

Abstract: A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field.

Abstract: An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.

Abstract: Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD.

Abstract: The presence or absence of a property in a computer subsystem is determined using a multiple input shift register (MISR). A subsystem device operates on predetermined test data to produce output data. The MISR operates on the output data to produce a final test value dependent on the output data. The property has a known final MISR value associated with the device under test and the test data. The MISR final test value is read and compared to the known final value for the property. If the two values are the same, the property exists in the system. In a second embodiment, a property from among a set of known possible properties or variations of a property is determined. In a specific application of the second embodiment, the length of a serial access memory (SAM) portion of a video random access memory (VRAM) is determined.

Abstract: Stored data for two different images superimposed on one another can be accessed simply and efficiently from the same VRAM. The SAM of the VRAM is divided into multiple-independent portions, each of which respond to its own independently controlled address counter. By loading the image data access into respective SAM portions, and switching data access between SAM portions at the SAM address rate, superimposed data of two different images can be displayed from the same VRAM.

Abstract: A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.

Abstract: A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.

Abstract: Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines.