Abstract: A field effect transistor includes two channel connection regions, a control region with at least two control sections, an active region that is formed as a projection of a mono crystalline substrate disposed between the channel connection regions and between two control region sections, and insulating regions that are electrically insulating and are disposed between the control region sections and the active region. The projection is isolated from the substrate at a base by an insulating material that is electrically insulating. The insulating material ends laterally at the projection in the mono crystalline substrate.

Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

Abstract: A resistless lithography method for fabricating fine stiuctures is disclosed. IN an embodiment, a semiconductor mask layer (HM) may be formed on a carrier material (TM, HM?) and a selective ion implantation (I) being effected in order to dope selected regions (1) of the semiconductor mask layer (HM). Wet chemical removal of the non doped regions of the semiconductor mask layer (HM) yields a semiconductor mask which can be used for further patterning. A simple and high precision resistless lithography method for structures smaller than 100 nm is obtained in this way.

Abstract: Patterning method, and field effect transistors An explanation is given of, inter alia, a patterning method, in which a filling material (22) with a T-shaped cross section is used as a mask during patterning in order to produce structures having sublithographic dimensions, in particular a double-fin field effect transistor.

Abstract: A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

Abstract: The invention relates to a method for fabricating a short channel field-effect transistor, comprising the steps of: forming a sublithographic gate sacrificial layer (3M), forming spacers (7S) at the side walls of the gate sacrificial layer (3M), removing the gate sacrificial layer (3M) to form a gate recess and forming a gate dielectric (10) and a control layer (11) in the gate recess. The result is a short channel FET with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

Abstract: A resistless lithography method for fabricating fine structures is disclosed. IN an embodiment, a semiconductor mask layer (HM) may be formed on a carrier material (TM, HM?) and a selective ion implantation (I) being effected in order to dope selected regions (1) of the semiconductor mask layer (HM). Wet chemical removal of the non doped regions of the semiconductor mask layer (HM) yields a semiconductor mask which can be used for further patterning. A simple and high precision resistless lithography method for structures smaller than 100 nm is obtained in this way.