Patents by Inventor Rodger Hughes

Rodger Hughes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11269790
    Abstract: A U-I/O card improves on traditional I/O cards by enabling configuration of each I/O channel on each U-I/O card to operate according to a desired signal type (e.g., AI, AO, DI, or DO). Thus, each I/O channel of a given U-I/O card may be coupled to any type of field device. The U-I/O card thus simplifies I/O network design, wiring, configuration, commissioning, redesign, and rewiring. The U-I/O card also improves space efficiency in marshalling cabinets and eliminates inefficient use of I/O cards relative to traditional I/O cards.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 8, 2022
    Assignee: EMERSON PROCESS MANAGEMENT POWER & WATER SOLUTIONS, INC.
    Inventors: Rodger Hughes, Richard W. Kephart, Jr., Steven J. Schilling, Timothy R. Piper
  • Publication number: 20200334173
    Abstract: A U-I/O card improves on traditional I/O cards by enabling configuration of each I/O channel on each U-I/O card to operate according to a desired signal type (e.g., AI, AO, DI, or DO). Thus, each I/O channel of a given U-I/O card may be coupled to any type of field device. The U-I/O card thus simplifies I/O network design, wiring, configuration, commissioning, redesign, and rewiring. The U-I/O card also improves space efficiency in marshalling cabinets and eliminates inefficient use of I/O cards relative to traditional I/O cards.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 22, 2020
    Inventors: Rodger Hughes, Richard W. Kephart, JR., Steven J. Schilling, Timothy R. Piper
  • Patent number: 10282250
    Abstract: Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bikram Banerjee, Anne Rodgers Hughes, John Michael MacLaren